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TMS320F28388D: Why the ESC RAM cannot be access by BWR command when it is defined as SM's

FENG ZHENG
Prodigy 10 points

Part Number: TMS320F28388D

Hi, we designed a ethercat slave with 28388D. The ESC RAM spanned from 0x1000 to 0x1010 is defined as a synchoronous manager in 3-buffer mode. When we enable the SM, neither the LWR nor BWR command can access this SM in OP mode. We have checked a series of status registers. The mode of ESC is in operation mode, no written action have been applied to the SM, and the EEPROM are well loaded. This question has puzzled me for a long time. Would you please give me some advice. Thanks a lot!