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Original question:

TMS320F28P650DH: Question about F28P65x CLB CLK

TMS320F28P650SH: CLBCLK Synchronization

Julia Li
Expert 4755 points

Part Number: TMS320F28P650SH

Hi Champs,

Now my customer have some question about CLB CLK.

  1. TRM shows CLB maximum frequency is 150MHz. Does this mean both maximum CLB Register Clock and maximum CLB TILE Clock are 150MHz?

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2. If customer use EPWM as CLB INPUT, synchronization is needed. But ePWM TZFRC and TZCLR events will sometimes be missed when EPWMCLKDIV is divide by 2 so we need to set EPWMCLK to 200MHz. If it needs to run in synchronous mode, the CLB Tile and Register clocks will be synchronized to a 200MHz EPWMCLK. It seems that this cannot meet the requirements for the CLB CLK. How can we solve this issue? Can we use 200MHz CLB Register clock and 100MHz Tile clock?

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Thanks!

 

Best Regards,

Julia