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F29H850TU: Interrupts on C29x

Wayne Huang
Genius 16795 points

Part Number: F29H850TU

Hi champs,

 

I am asking this for our customer.

From Chapter 3 Interrupts of C29x CPU Reference Guide : SPRUIY2A 

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1) Would you please explain in more detail the definition of term maskable and disableable here?

Does "maskable" just mean the ISR can be delayed and/or changed in priority?

2) What is HW latency for a RTINT if there is no other ISR? What is HW latency for a RTINT if this RTINT nesting another ISR of lower priority?

3) What is HW latency for a INT if there is no other ISR? What is HW latency for a INT if this INT nesting another ISR of lower priority?

  • +1
    TI__Mastermind 18425 points

    Wayne,

    Wayne Huang said:

    1) Would you please explain in more detail the definition of term maskable and disableable here?

    Does "maskable" just mean the ISR can be delayed and/or changed in priority?

    Maskable refers to the software configurability of the interrupt priority level and the ability to be nested-in, essentially.

    Disableable refers to the ability to enable or disable an interrupt using the DSTS.INTE bit within the CPU. This is different than the global enable/disable bit within the PIPE module. 

    Wayne Huang said:
    2) What is HW latency for a RTINT if there is no other ISR? What is HW latency for a RTINT if this RTINT nesting another ISR of lower priority?

    RTINT/NMI uses the HW RTINT stack and there is a fixed latency number, though it could be lesser cycles if not all the registers are saved/restored. This is automatic. 

    Wayne Huang said:
    3) What is HW latency for a INT if there is no other ISR? What is HW latency for a INT if this INT nesting another ISR of lower priority?

    INT uses an user-configurable SW stack, so the latency is truly dependent on the application including whether all the registers are saved/restored. This is done in SW.

    I have messaged you some more information. 

    Best Regards,

    Aishwarya