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TMS320F28379D-Q1: wrong documentation on SPI FIFO

Slobodan Gataric
Expert 1080 points

Part Number: TMS320F28379D-Q1

Dear Support,

I was reading the SPI chapter in the 379 TRM. FIFO expenation complelty confused me. I belive it is dead wrong. Paragraph "18.3.7 SPI FIFO Description":

6. Buffers. Transmit and receive buffers are each supplemented with a 16-word FIFO. The one-word transmit
buffer (SPITXBUF) of the standard SPI functions as a transition buffer between the transmit FIFO and shift
register. The one-word transmit buffer is loaded from transmit FIFO only after the last bit of the shift register
is shifted out.

Figure 18-6:

 image.png

 

Bold highlighted text above and Figure 18-6 are compleltly wrong.

SPITXBUF does not get loaded FROM FIFO, it loads FIFO! There is a big difference bewtween these two. User write up to 16 words to SPITXBUF without waiting on the SPI to clock the data out. 

I beleive the Figure 18-6 should be like this 

image.png

 

The FIFO is in betwen SPITXBUF and serial shift register not the other way arround. IIt is very strange that it is not just Figure 18-6, but text in the paragraph 18.3.7 matches the figure and both are wrong.

Is my understanding correct? If it is, TI should fix the documentation.

I was able to test it by writing wihtout any wait two different 16 bits words into SPITXBUFF and both words came out on MOSI pin.

 

 

Regards,

Gasha

 

  • 0
    TI__Mastermind 27320 points

    Hi Gasha,

    Thanks for your inquiry. Please allow another day for me to look into this for you.

    Best Regards,

    Allison

  • 0
    TI__Mastermind 27320 points

    Hi Gasha,

    The diagrams are showing what is happening internally in the hardware. Keep in mind, the FIFOs are not memory mapped or viewable - this is part of the peripheral hardware implementation. So from an external user perspective, you only need to use/interact with the RXBUF and TXBUF registers - the rest is taken care of behind the scenes.

    This is why you can write back to back and transmit both words. In software, you are writing to TXBUF. But in hardware, the data is going to the FIFO immediately and then shifted out via TXBUF into SPIDAT as needed.

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Expert 1080 points

    Yes, I figured that one out. This request is not about what I need to do. It is about fixing documentation. You did not confirm or deny that the documentation has a problem. The documentation says that SPITXBUF gets loaded from FIFO. That is not the case. It is the other way around. SPITXBUF loads FIFO. Do you agree with that? If you do, then you need to report documentation problem to documentation group, so it is fixed in the next version. I suggest changing the highlighted text above (in bold) to reflect that FIFO get loaded from SPITXBUF and not the other way around. Also, the figure 18-6 needs to be updated to reflect that. 

    This would be correct:

    The one-word transmit buffer (SPITXBUF) of the standard SPI functions as loader register to the transmit FIFO. The transmit FIFO is between SPITXBUF and shift register. The shift register is loaded from transmit FIFO after the last bit of the shift register is shifted out if the transmit FIFO is not empty.

    Do you think the text above is a correct explanation of how SPI transmit FIFO works? I never said FIFO is memory mapped. I understand it is not. 

    Gasha

  • 0 in reply to Slobodan Gataric
    TI__Mastermind 27320 points

    Hi Gasha, 

    Based on internal hardware design, the text and figures are correct. SPITXBUF does get loaded from the FIFO. This is taken care of in hardware, so from a user perspective, this detail may not be obvious.

    However, I do understand how there may be some confusion introduced based on this, so I will file a request to look into how to improve this section of documentation going forward. Thanks for your input here.

    Best Regards,

    Allison