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LAUNCHXL-F280049C: Troubleshooting the cause of ITRAP handler (loopInterrupt_illegalOperationHandler)

Part Number: LAUNCHXL-F280049C
Other Parts Discussed in Thread: SFRA

Dear TI Team,

I am working on as project related to digital buck boost converter. I believe I configured the CMD file correctly as I can generate the code by combining the FLASH BANKS  8 9 10 11 (FLASH_BANK0_SEC8_9_10_11). Before combining them to one I was receving linker error cuz of no space to fit in code.

Now the issue is during initialisation inside main block upon entering DCL_setup() and just when trying to execute  BUCK_ DCL_UPDATE(&BUCK_ctrl);  I am having ITRAP handler executing in loop.
 
Could you please help me in finding the cause of this issue. My flash.cmd file is as follows. I am using Lauchpad_F280049C
 
SECTIONS
{
   codestart        : > BEGIN, ALIGN(8)
   .text            : >> FLASH_BANK0_SEC8_9_10_11,   ALIGN(8)
   .cinit           : > FLASH_BANK0_SEC1,  ALIGN(8)
   .switch          : > FLASH_BANK0_SEC1,  ALIGN(8)
   .reset           : > RESET,                  TYPE = DSECT /* not used, */

   .stack           : > RAMM1

#if defined(__TI_EABI__)
   .init_array      : > FLASH_BANK0_SEC1,  ALIGN(8)
   .bss             : > RAMLS0LS1
   .bss:output      : > RAMLS0LS1
   .bss:cio         : > RAMLS0LS1
   .data            : > RAMLS0LS1
   .sysmem          : > RAMGS2
   .const           : > FLASH_BANK0_SEC4,  ALIGN(8)
#else
   .pinit           : > FLASH_BANK0_SEC1,  ALIGN(8)
   .ebss            : > RAMLS5
   .esysmem         : > RAMLS5
   .cio             : > RAMLS0
   .econst          : > FLASH_BANK0_SEC4,  ALIGN(8)
#endif

    ramgs0 : > RAMGS0GS1
    ramgs1 : > RAMGS0GS1

    /*  Allocate IQ math areas: */
    IQmath          : > FLASH_BANK0_SEC1, ALIGN(8)
    IQmathTables    : > FLASH_BANK0_SEC2, ALIGN(8)

    GROUP
    {
        .TI.ramfunc
        {
            -l sfra_f32_tmu_eabi.lib
        }
        ramfuncs

    }   LOAD = FLASH_BANK0_SEC1,
        RUN = RAMGS0GS1,
        LOAD_START(RamfuncsLoadStart),
        LOAD_SIZE(RamfuncsLoadSize),
        LOAD_END(RamfuncsLoadEnd),
        RUN_START(RamfuncsRunStart),
        RUN_SIZE(RamfuncsRunSize),
        RUN_END(RamfuncsRunEnd),
            ALIGN(4)

    SFRA_F32_Data   : > RAMLS0LS1, ALIGN = 64

    FPUmathTables   : > FLASH_BANK0_SEC12

    .scratchpad     : > RAMLS0LS1
    .bss_cla        : > RAMLS0LS1
    controlVariables    : > RAMLS0LS1

    .const_cla      :   LOAD = FLASH_BANK1_SEC8_9_10,
                        RUN = RAMLS2LS3LS4LS5,
                        RUN_START(Cla1ConstRunStart),
                        LOAD_START(Cla1ConstLoadStart),
                        LOAD_SIZE(Cla1ConstLoadSize)

    GROUP
    {
          isrcodefuncs
        dclfuncs
    }   LOAD = FLASH_BANK1_SEC8_9_10,
        RUN =  RAMLS2LS3LS4LS5,
        LOAD_START(isrcodefuncsLoadStart),
        LOAD_SIZE(isrcodefuncsLoadSize),
        LOAD_END(isrcodefuncsLoadEnd),
        RUN_START(isrcodefuncsRunStart),
        RUN_SIZE(isrcodefuncsRunSize),
        RUN_END(isrcodefuncsRunEnd),
            ALIGN(4)

    /* CLA specific sections */
    Cla1Prog :  LOAD = FLASH_BANK1_SEC8_9_10,
                RUN = RAMLS2LS3LS4LS5,
                LOAD_START(Cla1ProgLoadStart),
                RUN_START(Cla1ProgRunStart),
                LOAD_SIZE(Cla1ProgLoadSize),
                    ALIGN(4)

}