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Concerto Cortex-M3 MPU

I'm trying to port code that has run on various different Cortex-M3 microcontrollers to the Concerto Cortex-M3 core using CCS v5.1.

For some reason, I seem to be unable to write to the memory mapped MPU registers MPUCTRL (0xE000ED94), MPUBASE (0xE000ED9C) and MPUATTR (0xE000EDA0). The code is running in Privileged mode and I can write to the System Control Block, System Timer and NVIC registers without any problems.

If I use the debugger 'Memory Browser; or 'Registers' view, then I can modify the values of the registers as expected.

Have I missed something?

  • James,

    I just tried this myself and I am having the same issue.  Let me dig a little deeper and I'll get back to you as soon as I have a solution.

    Trey

  • James,

    I checked around and it turns out the MPU is not connected on F28M35x devices.  It is unclear to me if this is an errata or a "feature".

    The only place this appears to be documented is in section 27.1 of the Concerto Technical Reference Manual.  There is a small note that says "This feature is disabled on F28M35x devices".  I know this is probably very frustrating to you and I feel the same way.  There are numerous sections in the TRM that describe the MPU, so naturally one would think this hardware is there and functional.  I will get the documentation updated to more clearly show the MPU is disabled as well as checking in to whether this is a bug or not.

    Stay tuned for more information,

    Trey

  • James,

    I got some more information.  This is in fact a bug, but it hasn't been added to the errata yet (should be added soon).  This will be fixed in the next revision of Concerto.

    Trey

  • Thanks for looking into this Trey. Is there a schedule for release of the next revision?

    James.

  • Concerto Rev. A should be released in Q4 2012.

    Trey

  • Trey,

    Does this affect the ability to enable S0-S7 ram for use with the Cortex M3  processor on the Concerto?

    Thanks,

    Pat

     

  • Pat,

    No, Shared RAMs have been working on both cores from day 1.

    Trey

  • Trey,

    Thanks for the response. What is the initialization procedure to activate S0-S7 on the Concerto?

    Pat

     

  • Pat,

    Please refer to the RAM_Management example in the Dual examples folder.

    Trey

  • Trey,

    I'm missing how the physical ram locations get tied to the labels SHARERAMS0 and SHARERAMS2. In the example, I see that DATA_SECTIONs were established to link arrays to the labels, but I don't see any reference to either the array or the label in the GEL file. But the map file shows that the ram has been allocated. Could you explain how that happens?

    Thanks,

    Pat

     

  • Pat,

    Try opening up the linker command file for the project.  I believe it is F28M35x_generic_wshared_M3_FLASH.cmd.  Inside you'll find the memory declaration:

    /* Shared RAM */
        S0 (RWX)        : origin = 0x20008000, length = 0x2000
        S1 (RWX)        : origin = 0x2000A000, length = 0x2000
        S2 (RWX)        : origin = 0x2000C000, length = 0x2000
        S3 (RWX)        : origin = 0x2000E000, length = 0x2000
        S4 (RWX)        : origin = 0x20010000, length = 0x2000
        S5 (RWX)        : origin = 0x20012000, length = 0x2000
        S6 (RWX)        : origin = 0x20014000, length = 0x2000
        S7 (RWX)        : origin = 0x20016000, length = 0x2000

    and the association of those labels with the memory sections:

        SHARERAMS0  : > S0
        SHARERAMS1  : > S1
        SHARERAMS2  : > S2
        SHARERAMS3  : > S3
        SHARERAMS4  : > S4
        SHARERAMS5  : > S5
        SHARERAMS6  : > S6
        SHARERAMS7  : > S7

    Trey

  • Thanks Trey,

    I found the file, but had to search using Explorer to locate. The .cmd file does not show in the project folder and cannot be accessed using CCS as it is part of the mware tool section that buried in the include directory. The .cmd file memory configuration is apparently handled by CCS as there is a warning not to change the .cmd file directly, but to make modifications in the CCS project. I have not been able to locate any such memory configuration capability in CCS.

    How is that done?

    Thanks very much for your help.

    Pat

     

  • Pat,

    The linker command files must be manually opened and modified right now.  There is no memory configuration tool in CCS.

    We could have included linker files in each project, but we elected to link them to the project using the project properties.  This allows us to have different build configurations which use different linker command files.  The build configurations allow us to build a single project to run from RAM or flash both with and without the debugger. 

    Try right clicking the project, build properties, C2000 Linker, File Search Path and you'll see where the command files get pulled in.  Change the build configuration at the top of the window to see the linker file change.

    Trey

  • Trey,

    My interest is in the m3 side. I can see the .cmd file under file search path, but don't see how to edit it unless I just open the file using "open file". I guess that how it is done?

    My need is to expand my memory beyond the C2 and C3 (current .bss section), adding S0-S7 to the .bss section such that I will have contiguous memory in order to increase my heap size and stack sizes for my many tasks. I tried modifying the .cmd file, adding S0 to C2 and C3 (adding 2000 to the length of the C2_C3 section and commenting out S0. This did not change my .map file.

    I am building on the PHY example that TI provided. What do I need to do here to expand my memory.

    Thanks again,

    Pat

     

  • Yes, the files can't easily be edited unless they are opened manually.

    It sounds like you've got the right idea when it comes to editing the linker files.  I suspect you just weren't editing the same linker file the project was using.  If you don't see a cmd file in the linker file search path, look in the project next to the c and h files for the cmd file.  I think several of the ethernet examples use a project specific linker file as they have a rather large memory footprint.

    Trey

  • Trey,

    I apparently have two map files, a concerto_m3_tx.map and a flash_m3.map. The flash map does contain the change that I placed in the F28M35H52C1_m3_FreeRTOS.cmd file. Is this normal? Should I try to delete one of the map files?

    Thanks,

    Pat

     

  • Trey,

    I did delete the concerto map as it's date code was pretty old. It dd not make any difference.

    I have been experimenting with increasing my heap size (only change) to 10000, then 9000, then back to 8000. Whenever I increase it beyond 8000, my program will not run. Is there some other configuration / initialization that I need to do?

    Thanks for all your help,

    Pat

     

  • Pat,

    The MPU on the initial Concerto devices is disabled.  I'm not sure if they plan to enable this on future revisions of the silicon.

    Sounds like the concerto map file was from a much earlier build.  Certainly you can disregard that file.  My advice would be to look at the build console in the bottom of CCS.  This will tell you the exact linker files the linker is being called with.

    I don't think there is any special initialization you need to do before using the heap.  Our startup code should handle that.  Can you step through your code and find out where things are falling apart?

    Trey

  • Trey,

    What is the latest update on the silicon revision, still at the end of this year?

    Thanks,

    Pat

     

  • Trey,

    I tried to add initialization to the GEL file using information from the data sheet for the f28m35h52c1. Here is the updated file segment:

    hotmenu M3_Ram_Init()
    {
        *(unsigned long *)0x400FB240 |= 0x00000055; /* Initialize C0, C1, C2, C3 RAM's */ 
        *(unsigned long *)0x400FB250 |= 0x00000055; /* Initialize S0, S1, S2, S3 RAM's */  /////
          
        *(unsigned long *)0x400FB260 |= 0x00000001; /* Initialize MtoC MSG RAM's */
        while(*(unsigned long *)0x400FB270 != 0x55);
        while(*(unsigned long *)0x400FB288 != 0x01);

    Is that second line correct? Would I change the address to 0x400FB260 for S4-S7?

    Thanks,

    Pat