Part Number: TMS320F28379D
Other Parts Discussed in Thread: PMP23338
Dear Team,
Our current Vienna Rectifier system is designed to convert a 115Vac (400 Hz) input to a regulated 380Vdc output, During testing involving a 50ms input power interruption, the DSP is maintained active by hold-up capacitors. However, we have observed a 200ms delay between the resumption of the AC grid power and the recommencement of PWM signal generation by the DSP.
Note: To prevent unsafe operation during undervoltage conditions, PWM generation is tripped if the RMS input voltage, as calculated by the Power Line Analyzer function, falls below a 70Vac threshold.
Debugging:
1) we instrumented the code to toggle GPIO 23 immediately upon the calculated RMS voltage exceeding the 70Vac threshold. This confirmed that the Power Line Analyzer requires approximately 200ms to compute a valid RMS voltage above the threshold after the power returns . Note: The If condition was include in the main function.
2) To further investigate the root cause of this latency, the slewupdate count parameter was reduced from 100 to 15. This modification resulted in a significant improvement in the Power Line Analyzer's RMS calculation time, reducing the delay for the VRMS>70Vac condition to be met to approximately 10ms.
How does the reduction in the slewupdate count parameter specifically affect the calculation time of the RMS input voltage within the Power Line Analyzer function? We require clarification on the mechanism linking this parameter to the observed latency reduction.
