Part Number: TMS320F28377D
Hi Expert,
I have some cunfsion on the adc ex6 soc continuous dma example.
First is about triggering for ADCA.
Seems that the SCO0 is triggered by PWM, and the rest of the SOC are triggered by software.
//
// Configure SOCs channel no. & acquisition window.
// Trigger SCO0 from EPWM2SOCA.
// Trigger all other SOCs from INT1 (EOC on SOC0).
//
ADC_setupSOC(adcBase, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM2_SOCA,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER1, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER2, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER3, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER4, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER5, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER6, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER7, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER8, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER9, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER10, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER11, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER12, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER13, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER14, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
ADC_setupSOC(adcBase, ADC_SOC_NUMBER15, ADC_TRIGGER_SW_ONLY,
(ADC_Channel)channel, acqps);
From the comment , I assumes those SOC are triggered by SW in the ISR, however, I didn't see the ADC trigger in the ADC ISR
//
// adcA1ISR - This is called after the very first conversion and will disable
// the ePWM SOC to avoid re-triggering problems.
//
#pragma CODE_SECTION(adcA1ISR, ".TI.ramfunc");
__interrupt void adcA1ISR(void)
{
//
// Remove ePWM trigger
//
EPWM_disableADCTrigger(EPWM2_BASE, EPWM_SOC_A);
//
// Disable this interrupt from happening again
//
Interrupt_disable(INT_ADCA1);
//
// Acknowledge interrupt
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}
So how are SOC1-SOC15 triggered?
Second is DMA. The Configuration are like below:
DMA_configAddresses(DMA_CH1_BASE, (uint16_t *)&adcADataBuffer,
(uint16_t *)ADCARESULT_BASE);
//
// Perform enough 16-word bursts to fill the results buffer. Data will be
// transferred 32 bits at a time hence the address steps below.
//
DMA_configBurst(DMA_CH1_BASE, 16, 2, 2);
DMA_configTransfer(DMA_CH1_BASE, (RESULTS_BUFFER_SIZE >> 4), -14, 2);
DMA_configMode(DMA_CH1_BASE, DMA_TRIGGER_ADCA2,
(DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_DISABLE |
DMA_CFG_SIZE_32BIT));
From the src_addr and dest_addr, I am assuming this DMA is to match the adc result register to a buffer. The adc result registers is 16bit*16 (result0-result15), however, the word length is set as 32-bit and the brust size is 16, in each brust the src_addr would cover the range of 32bit*16, which does not aligns with the adc results length.
And also the transfer step is confusing. In each Burst, the src_addr is moved forward by (16-1)*2 = 30, if we want to reset src_addr to the adc result0 after each burst, we should set the transfer_step as -30, right? But it's set as -14 in the example. I can not think of why it's set as -14.
Could you please help clarifying above confusion?
Regards,
Hang

