• State Resolved
  • Locked Locked
  • Replies 15 replies
  • Answers 1 answer
  • Subscribers 83 subscribers
  • Views 362 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28P650DK: Flash_initModule leading to illegal trap

Bhanu Surya Prasad A
Prodigy 10 points

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: TMS320F28377S

 

Hi TI Team,

Currently, I am developing a bootloader for TMS320F28P650DK9 following the flow outlined below (which is alredy there for TMS320F228P77s). During boot main initialization when it entering to Flash_initModule, the process enters an illegal trap and does not recover from it. I need support to unblock this situation belw added code start branch file and linker command files ,

 

 

 

Also addind the linker command file and code start branch file below :

Linker command file :

MEMORY
{
   BEGIN            : origin = 0x080000, length = 0x000002  // Update the codestart location as needed

   BOOT_RSVD        : origin = 0x000002, length = 0x0001AF     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x0001B1, length = 0x00024F
   RAMM1            : origin = 0x000400, length = 0x000400

   RAMD0            : origin = 0x00C000, length = 0x002000
   RAMD1            : origin = 0x00E000, length = 0x002000
   RAMD2            : origin = 0x01A000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection
   RAMD3            : origin = 0x01C000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection
   RAMD4            : origin = 0x01E000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection
   RAMD5            : origin = 0x020000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection

   RAMLS01234         : origin = 0x008000, length = 0x002800
   //RAMLS1           : origin = 0x008800, length = 0x000800
   //RAMLS2           : origin = 0x009000, length = 0x000800
    //RAMLS3          : origin = 0x009800, length = 0x000800
   //RAMLS4           : origin = 0x00A000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800
   RAMLS8           : origin = 0x022000, length = 0x002000  // When configured as CLA program use the address 0x4000
   RAMLS9           : origin = 0x024000, length = 0x002000  // When configured as CLA program use the address 0x6000

   // RAMLS8_CLA    : origin = 0x004000, length = 0x002000  // Use only if configured as CLA program memory
   // RAMLS9_CLA    : origin = 0x006000, length = 0x002000  // Use only if configured as CLA program memory

   RAMGS0           : origin = 0x010000, length = 0x002000
   RAMGS1           : origin = 0x012000, length = 0x002000
   RAMGS2           : origin = 0x014000, length = 0x002000
   RAMGS3_4           : origin = 0x016000, length = 0x004000
   //RAMGS4           : origin = 0x018000, length = 0x002000

   /* Flash Banks (128 sectors each) */
   //FLASH_BANK0     : origin = 0x080002, length = 0x007FFE  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   //BOOT_FLASH       : origin = 0x080002, length = 0x007FFE

   BOOT_FLASH        : origin = 0x080002, length = 0x007FFE    /* on-chip Flash */
   APP_FLASH         : origin = 0x088000, length = 0x018000    /* on-chip Flash */

   FLASH_BANK1     : origin = 0x0A0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   FLASH_BANK2     : origin = 0x0C0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   // FLASH_BANK3     : origin = 0x0E0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   // FLASH_BANK4     : origin = 0x100000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection

 

   CPU1TOCPU2RAM    : origin = 0x03A000, length = 0x000400
   CPU2TOCPU1RAM    : origin = 0x03B000, length = 0x000400

   CLATOCPURAM      : origin = 0x001480,   length = 0x000080
   CPUTOCLARAM      : origin = 0x001500,   length = 0x000080
   CLATODMARAM      : origin = 0x001680,   length = 0x000080
   DMATOCLARAM      : origin = 0x001700,   length = 0x000080

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002
}


SECTIONS
{
   codestart        : > BEGIN
   .text            : >> APP_FLASH, ALIGN(8)
   .cinit           : > APP_FLASH, ALIGN(8)
   .switch          : > APP_FLASH, ALIGN(8)
   .reset           : > RESET, TYPE = DSECT /* not used, */

   .stack           : > RAMM1
#if defined(__TI_EABI__)
   .bss             : > RAMLS9
   .bss:output      : > RAMLS9
   .init_array      : > APP_FLASH, ALIGN(8)
   .const           : > APP_FLASH, ALIGN(8)
   .data            : > RAMLS7 | RAMLS8
   .sysmem          : > RAMLS5
#else
   .pinit           : > APP_FLASH, ALIGN(8)
   .ebss            : >> RAMLS5 | RAMLS6
                       START(_start_ebss)
                       END(_end_ebss)

   .econst          : > APP_FLASH, ALIGN(8)
   .esysmem         : > RAMLS5
#endif

   ramgs0 : > RAMGS0, type=NOINIT
   ramgs1 : > RAMGS1, type=NOINIT
   ramgs2 : > RAMGS2, type=NOINIT

   MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
   MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT

 /*boot memory allocation */
   boot_cinit
   {

      -l FAPI_F28P65x_EABI_v3.00.02.lib (.cinit)
         boot_main.obj(.cinit)
         boot_hwinit.obj(.cinit)
         boot_flash.obj(.cinit)
         boot_flash.obj(.econst)

   } > BOOT_FLASH

    boot_start
    {
          entry.obj (.text)
          boot_main.obj(.text)
          boot_hwinit.obj(.text)
          boot_flash.obj(.text)

    } > BOOT_FLASH

   boot_flash_lib :
   {
       -l FAPI_F28P65x_EABI_v3.00.02.lib (.econst)
       -l FAPI_F28P65x_EABI_v3.00.02.lib (.text)

   } LOAD = BOOT_FLASH,
     RUN = RAMLS01234,
     LOAD_START(_boot_flash_code_load_start),
     LOAD_SIZE(_boot_flash_code_size),
     RUN_START(_boot_flash_code_run_start)


   .data_boot
   {
           entry.obj (.data)
           boot_main.obj (.data)
           boot_hwinit.obj (.data)
           boot_flash.obj(.data)
           -l FAPI_F28P65x_EABI_v3.00.02.lib (.data)

   } > RAMM1

   .ebss_boot
   {
           entry.obj (.ebss)
           boot_main.obj (.ebss)
           boot_hwinit.obj (.ebss)
           boot_flash.obj(.ebss)
           -l FAPI_F28P65x_EABI_v3.00.02.lib (.ebss)

   } > RAMM1

 /* Allocate program areas: */
  // bootstrap
  // {
  //       entry.obj (.text)
  //  // - l FAPI_F28P65x_EABI_v3.00.02.lib (.cinit)
  //
  // } > APP_FLASH //0x088000

 


   #if defined(__TI_EABI__)
       .TI.ramfunc : {} LOAD = APP_FLASH,
                        RUN = RAMGS3_4,//RAMLS01234,
                        LOAD_START(RamfuncsLoadStart),
                        LOAD_SIZE(RamfuncsLoadSize),
                        LOAD_END(RamfuncsLoadEnd),
                        RUN_START(RamfuncsRunStart),
                        RUN_SIZE(RamfuncsRunSize),
                        RUN_END(RamfuncsRunEnd),
                        ALIGN(8)
   #else
       .TI.ramfunc : {} LOAD = APP_FLASH,
                        RUN = RAMGS3_4,
                        LOAD_START(_RamfuncsLoadStart),
                        LOAD_SIZE(_RamfuncsLoadSize),
                        LOAD_END(_RamfuncsLoadEnd),
                        RUN_START(_RamfuncsRunStart),
                        RUN_SIZE(_RamfuncsRunSize),
                        RUN_END(_RamfuncsRunEnd),
                        ALIGN(8)
   #endif

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

 

 

Code Start branch file :

***********************************************************************

     .global boot_main
     .global _entry
     .global __stack_boot
     .global _bootstrap_main
     .global _exit


     .global _start_ebss
     .global _end_ebss
****************************************************************************


****************************************************************************
* Declare the stack.  Size is determined by the linker option -stack.  The *
* default value is 1K words.                                               *
****************************************************************************
__stack_boot:    .usect    ".stack",0

****************************************************************************
*  INITIALIZE RESET VECTOR TO POINT AT _c_int00                            *
****************************************************************************
    .sect .reset
    .long _entry

    .text


****************************************************************************
* FUNCTION DEF : _bootstrap_main                                               *
*                                                                          *
****************************************************************************
_bootstrap_main:    .asmfunc
****************************************************************************
*  CALL USER'S PROGRAM                                                     *
****************************************************************************
    LB      _c_int00            ; execute TI init routines
    ;LCR        _exit
    LB      ExitBoot
    .endasmfunc
****************************************************************************
****************************************************************************
* FUNCTION DEF : _entry                                                  *
*                                                                          *
****************************************************************************
_entry:    .asmfunc
****************************************************************************
*  INITIALIZE STACK POINTER.                                               *
****************************************************************************
    MOV      SP,#__stack_boot        ; set to beginning of stack space

****************************************************************************
* INITIALIZE STATUS BIT FIELDS *NOT* INITIALIZED AT RESET                  *
****************************************************************************
    SPM    0            ; set product shift to 0

****************************************************************************
* SETTING THESE STATUS BITS/REGISTER TO RESET VALUES.  IF YOU RUN          *
* _c_int00 FROM RESET, YOU CAN REMOVE THIS CODE                            *
****************************************************************************
    CLRC    PAGE0            ; use stack addressing mode
    MOVW    DP,#0            ; initialize DP to point at low 64K
    CLRC    OVM                 ; turn off overflow mode

    ASP                ; ensure SP is aligned
****************************************************************************
*  CALL USER'S PROGRAM                                                     *
****************************************************************************
     LCR boot_main            ; execute boot_main()
     LB _bootstrap_main
        .endasmfunc
****************************************************************************

WD_DISABLE  .set  1    ;set to 1 to disable WD, else set to 0

    .ref _c_int00
    .ref main
    .global code_start
    .global ExitBoot

***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************

    .sect "codestart"
    .retain

code_start:
    .if WD_DISABLE == 1
        LB wd_disable       ;Branch to watchdog disable code
    .else
        LB _c_int00         ;Branch to start of boot._asm in RTS library
    .endif


;end codestart section

***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
    .if WD_DISABLE == 1

    .text
wd_disable:
    SETC OBJMODE        ;Set OBJMODE for 28x object code
    EALLOW              ;Enable EALLOW protected register access
    MOVZ DP, #7029h>>6  ;Set data page for WDCR register
    MOV @7029h, #0068h  ;Set WDDIS bit in WDCR to disable WD
    EDIS                ;Disable EALLOW protected register access
    ;LB _c_int00         ;Branch to start of boot._asm in RTS library
    LCR _entry           ;main in main file here main is there previously

 ; Cleanup and exit.  At this point the EntryAddr
; is located in the ACC register
    LB  ExitBoot
    .endif

;end wd_disable

;-----------------------------------------------
; ExitBoot
;-----------------------------------------------
;-----------------------------------------------
;This module cleans up after the boot loader
;
; 1) Make sure the stack is deallocated.
;    SP = 0x400 after exiting the boot
;    loader
; 2) Push 0 onto the stack so RPC will be
;    0 after using LRETR to jump to the
;    entry point
; 2) Load RPC with the entry point
; 3) Clear all XARn registers
; 4) Clear ACC, P and XT registers
; 5) LRETR - this will also clear the RPC
;    register since 0 was on the stack
;-----------------------------------------------

ExitBoot:

__stack:    .usect ".stack",0

;-----------------------------------------------
;   Insure that the stack is deallocated
;-----------------------------------------------

    MOV SP,#__stack

;-----------------------------------------------
; Clear the bottom of the stack.  This will endup
; in RPC when we are finished
;-----------------------------------------------

    MOV  *SP++,#0
    MOV  *SP++,#0

;-----------------------------------------------
; Load RPC with the entry point as determined
; by the boot mode.  This address will be returned
; in the ACC register.
;-----------------------------------------------

    PUSH ACC
    POP  RPC

;-----------------------------------------------
; Put registers back in their reset state.
;
; Clear all the XARn, ACC, XT, and P and DP
; registers
;
; NOTE: Leave the device in C28x operating mode
;       (OBJMODE = 1, AMODE = 0)
;-----------------------------------------------
    ZAPA
    MOVL  XT,ACC
    MOVZ  AR0,AL
    MOVZ  AR1,AL
    MOVZ  AR2,AL
    MOVZ  AR3,AL
    MOVZ  AR4,AL
    MOVZ  AR5,AL
    MOVZ  AR6,AL
    MOVZ  AR7,AL
    MOVW  DP, #0

;------------------------------------------------
;   Restore ST0 and ST1.  Note OBJMODE is
;   the only bit not restored to its reset state.
;   OBJMODE is left set for C28x object operating
;   mode.
;
;  ST0 = 0x0000     ST1 = 0x0A0B
;  15:10 OVC = 0    15:13      ARP = 0
;   9: 7  PM = 0       12       XF = 0
;      6   V = 0       11  M0M1MAP = 1
;      5   N = 0       10  reserved
;      4   Z = 0        9  OBJMODE = 1
;      3   C = 0        8    AMODE = 0
;      2  TC = 0        7 IDLESTAT = 0
;      1 OVM = 0        6   EALLOW = 0
;      0 SXM = 0        5     LOOP = 0
;                       4      SPA = 0
;                       3     VMAP = 1
;                       2    PAGE0 = 0
;                       1     DBGM = 1
;                       0     INTM = 1
;-----------------------------------------------

    MOV  *SP++,#0
    MOV  *SP++,#0x0A0B
    POP  ST1
    POP  ST0

;------------------------------------------------
;   Jump to the EntryAddr as defined by the
;   boot mode selected and continue execution
;-----------------------------------------------

    LRETR

;eof ----------

    .end


;//
;// End of file.
;//

 

 
  • 0
    TI__Genius 15570 points

    Hello,

    Let me loop in a colleague to assist, please expect a reply tomorrow.

    Best,

    Matt 

  • 0 in reply to Matt Kukucka
    TI__Mastermind 27145 points

    Here's your boot flow as I understand it.

    code_start -> wd_disable==1 -> _entry -> init SP etc. -> boot_main (presume here's where you check if there's new FW) -> if No _bootstrap_main -> _c_int00 -> main() of App

    My understanding is you're running into an ITRAP inside boot_main in Flash_initModule().

    1. Flash_initModule() needs to execute from RAM. Is a memcpy from Flash to RAM done?

    2. The code at wd_disable - where is it located at? It seems to be part of .text which is in APP_FLASH. Seems a little odd to put it in there. Might work, but I would suggest making it more deterministic, given it's part of the bootloader.

    Thanks,

    Sira

  • 0 in reply to Sira Rao80
    Prodigy 10 points

    1. Flash_initModule() needs to execute from RAM. Is a memcpy from Flash to RAM done?

    Yes, earlier fnCopyFlashToRAM() is used to do the same thing, now i commented and directly used memcpy() function now it is not leading to illegal trap

    function inside below:

    static void boot_fnCopyFlashToRAM(void)
    {

    uint16_t *p_dst = (uint16_t*) &boot_flash_code_run_start;
    uint16_t *p_src = (uint16_t*) &boot_flash_code_load_start;
    uint32_t size = (uint32_t) &boot_flash_code_size;

     while (size)
     {
     *p_dst = *p_src;
     ++p_dst;
     ++p_src;
     --size;
     }


    }

    2. The code at wd_disable - where is it located at? It seems to be part of .text which is in APP_FLASH. Seems a little odd to put it in there. Might work, but I would suggest making it more deterministic, given it's part of the bootloader.

    I didn't find wd_disable in APP_FLASH section same checked in memory allocation window , below is the screen shot 

  • 0 in reply to Bhanu Surya Prasad A
    Prodigy 10 points

    With the same function happening illegal trap below is the screen shots in disassembly break point mode 

  • 0 in reply to Bhanu Surya Prasad A
    TI__Genius 15570 points

    Hello,

    Are you also copying the Flash API from Flash to RAM before calling Fapi_initializeAPI?

    Best,

    Matt

  • 0 in reply to Matt Kukucka
    Prodigy 10 points

    Hello , 

    At the beginning of main () in InitSysCtrl() i am copying code from flash to RAM using memcopy() function , again for Fapi_initializeAPI need to copy it in RAM ?

    How to do it, could you please suggest a way?

    I have tried keeping this function in TI RAM functions using #pragma but no use, still same happening. 

  • 0 in reply to Bhanu Surya Prasad A
    TI__Genius 15570 points

    Hello,

    It doesn't look like you're grouping the Flash API library in ramfuncs in your linker command file, but in separate sections (i.e. boot_flash_lib). Can you share your map file for the bootloader?

    Best,
    Matt

  • 0 in reply to Matt Kukucka
    Prodigy 10 points

    Hello,

    Please find the map file attached as .txt file for your information

     Mk2p5_VSC.txt

    Best regards,

    Bhanu Surya Prasad.A

  • 0 in reply to Bhanu Surya Prasad A
    TI__Genius 15570 points

    Hello,

    Are you copying boot_flash_lib from Flash to RAM? This linker section contains the code for the Flash API, including Fapi_initializeAPI.

    Best,

    Matt

  • 0 in reply to Matt Kukucka
    Prodigy 10 points

    Hello,

    please share a secured path so that i will upload my code so that you can see.

    As i previously told already doing memcpy() at the starting of the code by copying it to RAM, what else i need to do not sure ?

    Regards,

    Bhanu Surya Prasad.A

  • 0 in reply to Bhanu Surya Prasad A
    TI__Genius 15570 points

    Hello,

    That memcpy copies the .ti.ramfuncs section in your linker cmd file from Flash to RAM. You placed in the Flash API library in a separate section in your linker cmd file and will have to do a similar call for boot_flash_lib as well.

    extern uint32_t _boot_flash_code_load_start, _boot_flash_code_run_start, _boot_flash_code_size;
memcpy(&_boot_flash_code_run_start, &_boot_flash_code_load_start, (size_t)&_boot_flash_code_size);

    Best,
    Matt

  • 0 in reply to Matt Kukucka
    Prodigy 10 points

    Hello ,

    After adding the above condition also, no improvement still Fapi_initializeAPI() leading to illegal trap, below are the screen shots and map and command files for your verification,

    Mk2p5_VSC_mapfile.txt 

    Fullscreen VSC_memory_command_file.txt Download 
    MEMORY
{
   BEGIN            : origin = 0x080000, length = 0x000002  // Update the codestart location as needed

   BOOT_RSVD        : origin = 0x000002, length = 0x0001AF     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x0001B1, length = 0x00024F
   RAMM1            : origin = 0x000400, length = 0x000400

   RAMD0            : origin = 0x00C000, length = 0x002000
   RAMD1            : origin = 0x00E000, length = 0x002000
   RAMD2            : origin = 0x01A000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection
   RAMD3            : origin = 0x01C000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection
   RAMD4            : origin = 0x01E000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection
   RAMD5            : origin = 0x020000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection

   RAMLS01234         : origin = 0x008000, length = 0x002800
   //RAMLS1           : origin = 0x008800, length = 0x000800
   //RAMLS2           : origin = 0x009000, length = 0x000800
    //RAMLS3          : origin = 0x009800, length = 0x000800
   //RAMLS4           : origin = 0x00A000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800
   RAMLS8           : origin = 0x022000, length = 0x002000  // When configured as CLA program use the address 0x4000
   RAMLS9           : origin = 0x024000, length = 0x002000  // When configured as CLA program use the address 0x6000

   // RAMLS8_CLA    : origin = 0x004000, length = 0x002000  // Use only if configured as CLA program memory
   // RAMLS9_CLA    : origin = 0x006000, length = 0x002000  // Use only if configured as CLA program memory

   RAMGS0           : origin = 0x010000, length = 0x002000
   RAMGS1           : origin = 0x012000, length = 0x002000
   RAMGS2           : origin = 0x014000, length = 0x002000
   RAMGS3_4           : origin = 0x016000, length = 0x004000
   //RAMGS4           : origin = 0x018000, length = 0x002000

   /* Flash Banks (128 sectors each) */
   //FLASH_BANK0     : origin = 0x080002, length = 0x007FFE  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   //BOOT_FLASH       : origin = 0x080002, length = 0x007FFE

   BOOT_FLASH        : origin = 0x080002, length = 0x007FFE	/* on-chip Flash */
   APP_FLASH         : origin = 0x088000, length = 0x018000	/* on-chip Flash */

   FLASH_BANK1     : origin = 0x0A0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   FLASH_BANK2     : origin = 0x0C0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   // FLASH_BANK3     : origin = 0x0E0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   // FLASH_BANK4     : origin = 0x100000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection



   CPU1TOCPU2RAM    : origin = 0x03A000, length = 0x000400
   CPU2TOCPU1RAM    : origin = 0x03B000, length = 0x000400

   CLATOCPURAM      : origin = 0x001480,   length = 0x000080
   CPUTOCLARAM      : origin = 0x001500,   length = 0x000080
   CLATODMARAM      : origin = 0x001680,   length = 0x000080
   DMATOCLARAM      : origin = 0x001700,   length = 0x000080

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002
}


SECTIONS
{
   codestart        : > BEGIN
   .text            : >> APP_FLASH, ALIGN(8)
   .cinit           : > APP_FLASH, ALIGN(8)
   .switch          : > APP_FLASH, ALIGN(8)
   .reset           : > RESET, TYPE = DSECT /* not used, */

   .stack           : > RAMM1
#if defined(__TI_EABI__)
   .bss             : > RAMLS9
   .bss:output      : > RAMLS9
   .init_array      : > APP_FLASH, ALIGN(8)
   .const           : > APP_FLASH, ALIGN(8)
   .data            : > RAMLS7 | RAMLS8
   .sysmem          : > RAMLS5
#else
   .pinit           : > APP_FLASH, ALIGN(8)
   .ebss            : >> RAMLS5 | RAMLS6
                       START(_start_ebss)
                       END(_end_ebss)

   .econst          : > APP_FLASH, ALIGN(8)
   .esysmem         : > RAMLS5
#endif

   ramgs0 : > RAMGS0, type=NOINIT
   ramgs1 : > RAMGS1, type=NOINIT
   ramgs2 : > RAMGS2, type=NOINIT



 /*boot memory allocation */
   boot_cinit
   {

      -l FAPI_F28P65x_EABI_v3.00.02.lib (.cinit)
         boot_main.obj(.cinit)
         boot_hwinit.obj(.cinit)
         boot_flash.obj(.cinit)
         boot_flash.obj(.econst)

   } > BOOT_FLASH

    boot_start
    {
          entry.obj (.text)//entry //f28p65x_codestartbranch
          boot_main.obj(.text)
          boot_hwinit.obj(.text)
          boot_flash.obj(.text)

    } > BOOT_FLASH

   boot_flash_lib :
   {
 	  -l FAPI_F28P65x_EABI_v3.00.02.lib (.econst)
 	  -l FAPI_F28P65x_EABI_v3.00.02.lib (.text)

   } LOAD = BOOT_FLASH,
     RUN = RAMLS01234,
     LOAD_START(_boot_flash_code_load_start),
     LOAD_SIZE(_boot_flash_code_size),
     RUN_START(_boot_flash_code_run_start)


   .data_boot
   {
           entry.obj (.data) //entry //f28p65x_codestartbranch
           boot_main.obj (.data)
           boot_hwinit.obj (.data)
           boot_flash.obj(.data)
           -l FAPI_F28P65x_EABI_v3.00.02.lib (.data)

   } > RAMM1

   .ebss_boot
   {
           entry.obj (.ebss) //f28p65x_codestartbranch
           boot_main.obj (.ebss)
           boot_hwinit.obj (.ebss)
           boot_flash.obj(.ebss)
           -l FAPI_F28P65x_EABI_v3.00.02.lib (.ebss)

   } > RAMM1

 /* Allocate program areas: */
  // bootstrap
  // {
  //       entry.obj (.text)
  //  // - l FAPI_F28P65x_EABI_v3.00.02.lib (.cinit)
  //
  // } > APP_FLASH //0x088000


   fapi             : > BOOT_FLASH
   {
       --library = FAPI_F28P65x_EABI_v3.00.02.lib

   }, ALIGN(8)



  // #if defined(__TI_EABI__)
       .TI.ramfunc : {} LOAD = APP_FLASH,
                        RUN = RAMGS3_4,//RAMLS01234,
                        LOAD_START(RamfuncsLoadStart),
                        LOAD_SIZE(RamfuncsLoadSize),
                        LOAD_END(RamfuncsLoadEnd),
                        RUN_START(RamfuncsRunStart),
                        RUN_SIZE(RamfuncsRunSize),
                        RUN_END(RamfuncsRunEnd),
                        ALIGN(8)
   //#else
   //    .TI.ramfunc : {} LOAD = APP_FLASH,
   //                     RUN = RAMGS3_4,
   //                     LOAD_START(_RamfuncsLoadStart),
   //                     LOAD_SIZE(_RamfuncsLoadSize),
   //                     LOAD_END(_RamfuncsLoadEnd),
   //                     RUN_START(_RamfuncsRunStart),
   //                     RUN_SIZE(_RamfuncsRunSize),
   //                     RUN_END(_RamfuncsRunEnd),
   //                     ALIGN(8)
   //#endif



   MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM,                type=NOINIT
   MSGRAM_CPU1_TO_CPU2_COPY_TO_M1_RAM > CPU1TOCPU2RAM, type=NOINIT
   MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM,                type=NOINIT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

    Thanks & regards,

    Bhanu Surya Prasad.A

  • +1 in reply to Bhanu Surya Prasad A
    TI__Genius 15570 points

    Hi Bhanu,

    Apologies, I mixed up the order of the parameters in the memcpy() call. The destination address is first:

    extern uint32_t _boot_flash_code_load_start, _boot_flash_code_run_start, _boot_flash_code_size;
memcpy(&_boot_flash_code_run_start, &_boot_flash_code_load_start, (size_t)&_boot_flash_code_size);

    I tested this on my setup and verified it to work.

    Best,

    Matt

  • 0 in reply to Matt Kukucka
    Prodigy 10 points

    Hi Matt,

    Yeah, finally it worked for me, thanks a lot !

    I need one help for TMS320F28377S below is the ranges and lengths used for flash api programming, same i needed for TMS320F28P650DK, could you please help me?

    Erase Function:

ui32sectorAddress = 0x0C8000;

while (ui32SectorCount < 7)
{

//
// Execute an erase operation using the Flash API
//
// oReturnCheck = 0;
oReturnCheck = Fapi_issueAsyncCommandWithAddress(
Fapi_EraseSector, (uint32_t*) ui32sectorAddress);

//
// Wait until the Flash State Machine is ready
//
while (Fapi_checkFsmForReady() != Fapi_Status_FsmReady)
{
}

//
// Perform a blank check on the recently erased sector to ensure it was erased
//
// oReturnCheck = 0;
oReturnCheck = Fapi_doBlankCheck((uint32_t*) ui32sectorAddress, 0x4000,
&oFlashStatusWord);

//
// Check the Flash API status for an error
//
if (oReturnCheck != Fapi_Status_Success)
{
return false;
}
else
{
ui32sectorAddress += 0x08000;
ui32SectorCount++;
}

}

Program Function:

 uint16_t uiWord;

    if (uiLen < 8)
        uiWord = uiLen;
    else
        uiWord = 8;

    oFlashStatus = Fapi_getFsmStatus();
    //    oReturnCheck = 0;

    while (uiLen > 0)
    {
        oFlashStatus = 0;
        oReturnCheck = Fapi_issueProgrammingCommand((uint32*) DestAdrs, uiBuff,
                                                    uiWord, 0, 0,
                                                    Fapi_AutoEccGeneration);

        //
        // Wait until the Flash program operation is over
        //
        while (Fapi_checkFsmForReady() == Fapi_Status_FsmBusy)
            ;

        //
        // Check for an error
        //
        if (oReturnCheck != Fapi_Status_Success)
        {

            *uierr = CAN_mFLASH_WRITE_FAIL;
            return false;
        }
        else
        {
            *uierr = 0;
        }

        //
        // Read FMSTAT register contents to know the status of FSM after
        // program command to see if there are any program operation related errors
        //
        oFlashStatus = Fapi_getFsmStatus();

        while (oFlashStatus)
            ;

        DestAdrs += uiWord;
        uiBuff += uiWord;
        uiLen -= uiWord;
        if (uiLen < 8)
        {
            uiWord = uiLen;
        }
    }

    Regards,

    Bhanu Surya Prasad.A

  • 0 in reply to Bhanu Surya Prasad A
    TI__Genius 15570 points

    Hello,

    Can you open up a new thread on this issue so it gets routed to the intended expert? Apologies for the delay, the thread was closed so it didn't show up on my end.

    Best,

    Matt