Part Number: TMS320F28375D
Other Parts Discussed in Thread: C2000WARE
Hi All,
In the function, argument 1 was defined as 32 bytes, but after the function call, only the lower 16 bytes of argument 1 were referenced.
After changing the order of arguments 1 and 2, the reference register became one that supports 32 bytes, and the correct value could be accessed.
Why did the initial argument setting result in a register that could only reference the lower 16 bytes?
Best Regards,
Ito
Hi George,
Thank you for your reply.
Hi Alex,
Thank you for your help.
Even when the function flashErase(), which calls Fapi_setActiveFlashBank(), is located in the ".TI.ramfunc" section,
we observe the same behavior: execution branches to 0x3FE493 and then halts.
However, the same phenomenon was also observed when running the reference base software,
and in that case the flash was successfully updated, as shown below (a reset is performed after the operation).
(Flash contents after running the base software)
In the current software, the flash update does not occur.
Therefore, we suspect that a reset is being triggered during the flash erase operation.
(Flash contents after running the current software)
Best Regards,
Ito
Hi Alex,
By "base software" do you mean the flash programming example?
Yes, that's correct.
When you say you observe the same phenomenon do you mean the base software also results in a reset?
This reset is expected behavior because a reset process is performed after FLASH operation.
After execution halts, what are the values of the RESC (reset cause) and FMSTAT (flash module status) registers?
Hi Alex,
By placing the entire API library in the .TI.ramfunc section, we have begun to see signs of a solution.
We are currently executing a memcpy right before the FLASH operation function “setOtaBoot”, and we are verifying the process that stores all required functions in RAM.
Could you please let us know whether it is possible to place the entire API library into the .TI.ramfunc section?
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */
// BEGIN : origin = 0x080000, length = 0x000002
BEGIN : origin = 0x0B0000, length = 0x000002
RAMM0 : origin = 0x000123, length = 0x0002DD
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
// RAMLS2 : origin = 0x009000, length = 0x000800
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
// FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
// FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
// FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
// FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
// FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
// FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
// FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
// FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
// FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0002, length = 0x007F7E, fill = 0xffff /* on-chip Flash */
FLASHJ_OTA_BOOT_FUNC : origin = 0x0B7F80, length = 0x000070, fill = 0xffff /* on-chip Flash */
FLASHJ_PRGINFO : origin = 0x0B7FF0, length = 0x000010, fill = 0xffff /* on-chip Flash */
// FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
// FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
// FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
// FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
// RAMD1 : origin = 0x00B800, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000780
RAMD1_REPRO_CRCINF : origin = 0x00BF80, length = 0x000080 /*各種CRC演算結果、ベリファイ結果保持領域*/
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHJ PAGE = 0, ALIGN(8)
.text : >> FLASHJ PAGE = 0, ALIGN(8)
codestart : > BEGIN PAGE = 0, ALIGN(8)
OTA_BOOT_FUNC : > FLASHJ_OTA_BOOT_FUNC, PAGE = 0, ALIGN(8)
PROGINF : > FLASHJ_PRGINFO, PAGE = 0, ALIGN(8)
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.switch : > FLASHJ PAGE = 0, ALIGN(8)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
#if defined(__TI_EABI__)
.init_array : > FLASHJ, PAGE = 0, ALIGN(8)
.bss : > RAMLS3 | RAMLS4 | RAMLS5, PAGE = 1
.bss:output : > RAMLS3 | RAMLS4, PAGE = 0
.bss:cio : > RAMLS5, PAGE = 1
.data : > RAMLS3 | RAMLS4 | RAMLS5, PAGE = 1
.sysmem : > RAMLS2 | RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.const : > FLASHJ, PAGE = 0, ALIGN(8)
#else
.pinit : > FLASHJ, PAGE = 0, ALIGN(8)
.ebss : >> RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS10 | RAMGS0 | RAMGS1, PAGE = 1
.esysmem : > RAMLS2 | RAMLS5, PAGE = 1
.cio : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASHJ PAGE = 0, ALIGN(8)
#endif
Filter_RegsFile : > RAMGS0, PAGE = 1
SHARERAMGS0 : > RAMGS0, PAGE = 1
SHARERAMGS1 : > RAMGS1, PAGE = 1
SHARERAMGS2 : > RAMGS2, PAGE = 1
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASHJ,
RUN = RAMLS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASHJ,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#else
ramfuncs : LOAD = FLASHJ,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#endif
/* Allocate DMA-accessible RAM sections: */
DMARAML7 : > RAMGS13, PAGE = 1
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
REPRO_RESULT_RAMD1 > RAMD1_REPRO_CRCINF, type=NOINIT
/* The following section definition are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Best Regards,
Ito