Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: AMC0336
Hello,
I am trying to configure the SDFM module and I think the table specifying bit shift configuration is wrong:
(this is taken from SPRUIZ1B, page 4258)
The setup: I do my sigma-delta measurement with Sinc3 and OSR = 256. I apply the full range of the nominal U_min - U_max to my sigma delta module (AMC0336, about +- 1V) and I watch the result in SDDATA1 (specifically DATA32HI) live via debugger. When using the configuration of bit shift SH = 10, I get the results in range 0xC100 - 0x3F00, in decimal is 49 408 - 16 128, which in two's complement is -16 128 to +16 128. On the contrary when I try bit shift of 9, i get the range 0x8200 - 0x7E00, which in decimal is 33 280 - 32 256, which in two's complement is -32 256 to +32 256.
By using bit shift of 10 I seemingly get half the resolution. My assumption is that in the 26-bit intermediate register, there is 24 bits of actual data [for OSR = 256, sinc3 -> OSR^(sinc order) = 24], and the 2 MSB both represent the sign.
This is supported by the fact that the actual range of the measurement is said to be -2^24 up to +2^24:
By shifting the result by 10 bits we lose one more data bit then what is necessary and we are left with two identical sign bits at the first two MSB's. At least this corresponds to the behavior I observed. Please let me know your thoughts.
Best regards
Ondřej
