Part Number: TMS320F28335
Hello,
I have a question regarding external memory (XINTF) timing on the F28335.
In the TMS320F2833x Data Manual, Figure 6-23 "Example Read Access" shows two timing parameters: tsu(XD)-XRD and th(XD)-XRD.
My question is:
When does the CPU actually sample the data on the data bus?
Is the data latched at the th(XD)-XRD point or at the tsu(XD)-XRD point?
