This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28384D: PIE Safety Feature– Clarification and Implementation Approach

Part Number: TMS320F28384D

Hello,

For microcontroller safety compliance, I plan to implement the following PIE module safety mechanisms:

  1. PIE Double SRAM Hardware Comparison
    Question: Is a software-based implementation required to meet this safety requirement in our project?

  2. PIE: Software Test of SRAM
    Question: The register bit MemCfgRegs.DxTEST.bit.TEST_PIEVECT is available on the F280015x series but not on the F2838x controller. What is the recommended approach for implementing this test in software on F2838x? If possible, could you share any sample code or reference implementation?

 Thank you.

  • PIE1 is implemented in hardware. The behavior during a mismatch is documented in the MCU TRM.

    PIE2 needs to be implemented in software. We do not have an example specifically for PIE. The PIE vector tables on the F2838x MCU are not protected by parity, this is why there is no such bit on this device. On the F280015x, there is parity protection.