LAUNCHXL-F29H85X: interrupt performance ADC readings

Hi Jan,

Please see my response below:

Jan Bock said:

Due to the memory architecture in the ADC, you have to read all 16 result registers via DMA, otherwise you lose data. Can you confirm this?

JC: The end of conversion will signal the transfer of conversion data to the ADCRESULTS register.  If the old result is not read, then it will be overwritten.  This is the case regardless of the way the results are read, DMA or CPU access,

Jan Bock said:

With n=8 channels, I can execute all possible repeats and they are triggered and executed correctly. However, if I only sample n=2 channels, the number of repeats varies (e.g., with m=5 and n=2, it only samples once).

JC: Do you have a rough diagram of what you are trying to accomplish?  Might be helpful to see what the issue might be.

Jan Bock said:

s there a timing issue with the interrupts? If so, what is their maximum resolution? If there's another reason, please correct me. I've tested this with pin toggles in the interrupts, as I'm just setting up the eRAD module

JC: Yes, ERAD would be good tool to use for profiling the interrupt latency,  It typically takes about 17 cycles for the code to enter the interrupt but this all depends also on what other processes are running.

Regards,

Joseph