Hi,
I have ported the universal lab code to f28379d.
While running, the CPU gets stuck at Flash_initModule() function.
Looks like an issue with the memory map. I have defined __TI_EABI__
Please let me know what I can do to address this issue.
//#############################################################################
//
// FILE: dual_axis_f2837x_flash_lnk_cpu1.cmd.cmd
//
//#############################################################################
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C
MEMORY
{
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000123, length = 0x0002DD
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
/* RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 */ /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD0 : origin = 0x00B000, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
// RAMGS0 : origin = 0x00C000, length = 0x001000
// RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS0_1 : origin = 0x00C000, length = 0x002000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
/* RAMGS11 : origin = 0x017000, length = 0x000FF8 */ /* Uncomment for F28374D, F28376D devices */
/* RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 */ /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS1415 : origin = 0x01A000, length = 0x001FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
/* RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 */ /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
/* FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 */ /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RESET : origin = 0x3FFFC0, length = 0x000002
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
codestart : > BEGIN, ALIGN(4)
.text : >> FLASHA | FLASHB | FLASHC | FLASHD, ALIGN(4)
.cinit : > FLASHG, ALIGN(4)
.switch : > FLASHG, ALIGN(4)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM1
#if defined(__TI_EABI__)
.init_array : > FLASHG, ALIGN(8)
.bss : > RAMLS0 | RAMLS1, ALIGN(4)
.bss:output : > RAMLS0 | RAMLS1
.bss:cio : > RAMLS0 | RAMLS1
.data : > RAMLS0 | RAMLS1
.sysmem : > RAMLS0 | RAMLS1
/* Initalized sections go in Flash */
.const : > FLASHG, ALIGN(8)
#else
.pinit : > FLASHG, ALIGN(8)
.ebss : > RAMLS0 | RAMLS1
.esysmem : > RAMLS0 | RAMLS1
.cio : > RAMLS0 | RAMLS1
/* Initalized sections go in Flash */
.econst : > FLASHG, ALIGN(8)
#endif
MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
/* CLA specific sections */
#if defined(__TI_EABI__)
Cla1Prog : LOAD = FLASHF,
RUN = RAMLS4 | RAMLS5,
LOAD_START(Cla1funcsLoadStart),
LOAD_END(Cla1funcsLoadEnd),
RUN_START(Cla1funcsRunStart),
LOAD_SIZE(Cla1funcsLoadSize),
ALIGN(8)
#else
Cla1Prog : LOAD = FLASHF,
RUN = RAMLS4 | RAMLS5,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
ALIGN(8)
#endif
ClaData : > RAMLS3
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, type=NOINIT
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, type=NOINIT
/* SFRA specific sections */
SFRA_F32_Data : > RAMGS5, ALIGN = 64
sfra_data : > RAMGS5
#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS2
.scratchpad : > RAMLS2
.bss_cla : > RAMLS2
#if defined(__TI_EABI__)
.const_cla : LOAD = FLASHF,
RUN = RAMLS4,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
ALIGN(8)
#else
.const_cla : LOAD = FLASHF,
RUN = RAMLS4,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
ALIGN(8)
#endif
#endif //CLA_C
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASHE,
// RUN = RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3,
RUN = RAMGS0_1 | RAMGS2 | RAMGS3,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(4)
#else
.TI.ramfunc : {} LOAD = FLASHE,
// RUN = RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3,
RUN = RAMGS0_1 | RAMGS2 | RAMGS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
ALIGN(4)
#endif
GROUP
{
.TI.ramfunc
ramfuncs
dclfuncs
dcl32funcs
}
LOAD > FLASHG,
RUN > RAMGS1415,
LOAD_START(RamfuncsLoadStart),
LOAD_END(RamfuncsLoadEnd),
LOAD_SIZE(RamfuncsLoadSize),
RUN_START(RamfuncsRunStart),
RUN_END(RamfuncsRunEnd),
RUN_SIZE(RamfuncsRunSize),
ALIGN(8)
ctrlfuncs : LOAD > FLASHG,
RUN > RAMGS1415,
LOAD_START(loadStart_ctrlfuncs),
LOAD_END(loadEnd_ctrlfuncs),
LOAD_SIZE(loadSize_ctrlfuncs),
RUN_START(runStart_ctrlfuncs),
RUN_END(runEnd_ctrlfuncs),
RUN_SIZE(runSize_ctrlfuncs),
ALIGN(8)
// .binit : > FLASHG,
// ALIGN(8)
// .cinit : > FLASHA,
// ALIGN(8)
// .stack : > RAMM0
// .init_array : > FLASHA,
// ALIGN(8)
// .bss : > RAMD0
// .const : > FLASHA,
// ALIGN(8)
// .data : > RAMD0
// .switch : > FLASHA,
// ALIGN(8)
// .sysmem : > RAMD0
est_data : > RAMGS13,
LOAD_START(loadStart_est_data),
LOAD_END(loadEnd_est_data),
LOAD_SIZE(loadSize_est_data)
hal_data : > RAMD1,
LOAD_START(loadStart_hal_data),
LOAD_END(loadEnd_hal_data),
LOAD_SIZE(loadSize_hal_data)
user_data : > RAMD1,
LOAD_START(loadStart_user_data),
LOAD_END(loadEnd_user_data),
LOAD_SIZE(loadSize_user_data)
foc_data : > RAMD1,
LOAD_START(loadStart_foc_data),
LOAD_END(loadEnd_foc_data),
LOAD_SIZE(loadSize_foc_data)
sys_data : > RAMD1,
LOAD_START(loadStart_sys_data),
LOAD_END(loadEnd_sys_data),
LOAD_SIZE(loadSize_sys_data)
vibc_data : > RAMGS12,
LOAD_START(loadStart_vibc_data),
LOAD_END(loadEnd_vibc_data),
LOAD_SIZE(loadSize_vibc_data)
dmaBuf_data : > RAMGS12,
LOAD_START(loadStart_dmaBuf_data),
LOAD_END(loadEnd_dmaBuf_data),
LOAD_SIZE(loadSize_dmaBuf_data)
datalog_data : > RAMGS12,
LOAD_START(loadStart_datalog_data),
LOAD_END(loadEnd_datalog_data),
LOAD_SIZE(loadSize_datalog_data)
SFRA_F32_Data : > RAMGS12,
LOAD_START(loadStart_SFRA_F32_Data),
LOAD_END(loadEnd_SFRA_F32_Data),
LOAD_SIZE(loadSize_SFRA_F32_Data)
}
//===========================================================================
// End of file.
//===========================================================================

