Hello,
I would like to know what would be the maximum number of cycles penalty when two CPU (or CLA/DMA) are accessing a shared resource such as GSRAM, message RAM or peripheral bridges ?
Are we talking of one cycle or could it be more ?
Just trying to figure out the assumptions to take for our multicore justifications.
Best regards,
Clément
Hi Clement,
It depends on the operation being done, but the maximum should be 2 cycles for GSRAM:
The arbitration scheme is a little bit complicated for this device, the relevant documentation is below:
For example, if all of the below came in for the same GSRAM memory simultaneously:
The order they are accessed is the following:
Please upvote this response if it answers your question 
Best Regards,
Delaney
