TMS320F28P650SK: External clock source - crystal issue

Hi Johnny,

Let me look into this and get back to you by the end of the week.

Best Regards,

Aishwarya

Johnny,

What is the value of the CL (load capacitor) used? For a 10 MHz crystal, the acceptable ESR range is 12-24 pF, per device requirements. 

In addition, was the Rd rated with the crystal vendor to ensure it's able to properly absorb the excess drive level outputted by the MCU? 

Best Regards,

Aishwarya

Hi Aishwarya,

Thanks for helping look at this.

Customer is messing up now since they have two BOMs for different CL1 = CL2 mounted on PCB. One BOM with 18pF for CL1/2, and the other BOM with 22pF for CL1/2.

Would you kindly check what's the max. ESR for 18pF and 22pF CL1/CL2 respectively for a 10MHz crystal? 

Crystal vendor told that the ESR with 18/22pF (either one set) CL1/CL2 is about ~20 something Ohm, I need to reconfirm the exact value from customer. From DS., it seems ESR with ~2x Ohm is in the DS, looks fine.

Aishwarya Rajesh said:

In addition, was the Rd rated with the crystal vendor to ensure it's able to properly absorb the excess drive level outputted by the MCU? 

Crystal vendor told them that having Rd = 470 Ohm keeps the drive level keeps around 100 uW, they have calibrated it. However, I can't comment on that.

Do you see any problem on the clock setup in code ? I have double check on clocktree, it seems ok.

I feel like this issue is highly related to crystal stuff since when executing the line SysCtl_setClock(), scoping the X1 pin, 10MHz oscillating signal is gone, then stuck into the SysCtl_pullX1Counter(). What else could cause the issue ?

Thanks for any input.

Johnny

Hi Aishwarya,

Checked with customer. CL1 / CL2 value: 22pF ; Rd value: 470ohm ; ESR < 110 ohm.

Besides, have some new finding today.

We have the same board programmed with example sci_ex1_echoback in bit-field (device_support) and driverlib.

With bit-field example, the InitSysPll function is configured as below and also try with IMULT_40. Both (x32 / x40) work well for getting desired system clock, and the crystal on X1 could be measured in 10MHz.

 (example in bit-field)

However, with example in driverlib, it is stuck at NMI or SysCtl_pullX1Counter() function. With such test, we could tell the crystal HW is fine, something go wrong with the function or SETCLOCK_CFG.

SysCtl_setClock(DEVICE_SETCLOCK_CFG);

#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL  | SYSCTL_IMULT(40) | \
                                     SYSCTL_REFDIV(1) | SYSCTL_ODIV(2) | \
                                     SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
                                     SYSCTL_DCC_BASE_0)

I don't see the driverlib function violates any clock freq. defined in every stage. I also check with clock tree.

Do you see any issue with the driverlib in above? or there is flaw with SysCtl_setClock function bottom layer in sysctl.c?

Thanks for the support.

Regards,

Johnny

Johnny,

Assuming this is the code that ultimately calls the SysCtl_pollX1Counter(), where the code is getting stuck, can you observe the SysCtl registers line by line up until this point?

Can you confirm which C2000WARE is being used and ensure the latest is used? I unfortunately do not have the necessary hardware to test on my end, but will look into it further offline as well.

Best Regards,

Aishwarya