TMS320F28075: Reading input form floating pin

Part Number: TMS320F28075

Hi Experts,

My customer recently met a devices reseting issue, it turns out that the cause is the following code:

status = SPI_read();
if(status == "reset"){
   Watchog_Reset();
}

What they do is read from the SPI interface, which should be connected to a external chip, and then devicde if they should reset the F28075 immedately.

The problem is, the external SPI chip is actually deleted in the design, and therefore it does not exist on the board. The SPI pins are NC. Since the external chip is deleted, this piece of code should be deleted as well, however, it somehow remains in the project, and the project has been shipped for a long while.

The situation is that they've been reading from a NC SPI interface, and the result would depends on the voltage on the NC pins. For a long time, this SPI read always returns a result that do not branch to reset (status != "reset"), therefore, the reset is not triggered, and the board works fine.

Until recently, serveral cases has appeared where the F28075 is reseting periodcally, and the reset cause is the above code. As we find this problem in the software, they believe all shipped products would have the risk of run into this issue someday. Therefore, they need our help to prioritize and handles the shipped products.

  • How the voltage of the NC pin are determined? 
  • What factor would affect the voltage on NC pin? This may help them judge the risk of shipped products. (it's not necessary ot be a 100% relation, a trend is also ok) 
  • It there any changes in F28075 manufacture that may cuases a differece? For the time being, all device that's reseting are shipped in 2025 May. 

 

  • Hi,

    Please note that due to the holiday season, there may be some delay in responses. 

    Best Regards,
    Aishwarya

  • Hi Hang,

    Leaving a pin on the device floating is not recommended and means that the value read on the input at any moment cannot be predicted. There are many factors that can effect the logic level read on a floating pin, including:

    • Leakage current
    • Parasitic capacitance
    • Coupled noise from nearby pins and internal buses

    Do they have internal pull-ups enabled for this pin?

    Best Regards,

    Delaney

  • Hi Delaney,

    No, the internal pull-ups are not enabled, the pin is totally floating.

    I understand the that may factors can effect the logic level on the floating pin, however, is it possible to identify that some factors are batch related?

    The goal is to identify the device that have higher risk of reading high logic level on the specific floating, so that customer can prioritize on dealing with these shipped devices. 

    For example, assuming the higher leakage current the more likely to get a low level when reading a floating pin, do we have information on if certain batch of device would have higher leakage, so that we can marked them as higher risk?

    On the other hand, if all device share the same range/distribution of leakage current value, then the risk are the same for all devices on this perspective. We also need to convey the message that all devices has the same risk.

    Could you please help evaluating the risk on this perspective? Can we provide any information to help customer prioritize or we can only tell them all devices has the same risk?

  • Hi Hang,

    The only thing we can guarantee is that all the parts have been tested to meet the datasheet specs. There is unfortunately no correlation we can give them for the behavior; with a floating pin there is always a risk that a high logic level can be read in since this is based on environmental factors.

    Best Regards,

    Delaney

  • Hi Delaney,

    Adding one condition here. There are actually two GPIO included in the issue.

    The two GPIO are both floating as said. One GPIO is GPIO71, used as GPIO function, which we just discussed. The other GPIO58 is used as SPI MISO. 

    The condition of this issue is that  GPIO71 is high AND the SPI read returns a certain value.

    Compare the good board and the bad board, we have the below finding:

    1. The GPIO71 is always high on bad board, and is always low on good board, which is tested with a sdk example.

    2. The SPI read always returns the same value written, on good board and bad board. The RX FIFO would holds the same value as TX FIFO, like a loopback, except the loopback function s not actually enable.

    Although both GPIO71 and GPIO58 is floating, the behavior is different. How to explain the difference? Why the SPI would return the same value is RX pin is floating?

    In the meantime, although there is always a risk of reading a high logic level. The issue never occurs until recently. Tracking the BC of the bad devices, the oldest devices holds the BC of 36, which means is manufactured on 2023 June. Customer also shipped many devices manufactured from 2021 to 2023, but there is no issue on those device.

    Therefore, we are also investigating from the timeline perspective that what's changed around that time that might cause the difference in GPIO71

    We are aware of the changes from factory change from TSMC to lehi around 2023, however, there is one batch that comes from TSMC that has the bad devices (GPIO71 holds logic high value when floating). Therefore, this change might not be the cause. Is there any other changes around that time?  Any Idea from the time perspective?

    As you said 

    The only thing we can guarantee is that all the parts have been tested to meet the datasheet specs.

    Since the value of floating pin is not included in the specs, we don't do related test, right? Is there any test data related to floating pin we can share? If no youu may help confirming that we don't have it.

    Lastly,

    Customer is asking the GPIO's behavior related to temperature, do we have data(other than datasheet and TRM) to share or no? 

  • Hi Hang,

    Although both GPIO71 and GPIO58 is floating, the behavior is different. How to explain the difference? Why the SPI would return the same value is RX pin is floating?

    If both GPIO71 and GPIO58 are floating, they can both read to either high or low logic level at any time. There would be no way to explain the difference, this isn't unexpected behavior. 

    The RX FIFO would holds the same value as TX FIFO, like a loopback, except the loopback function s not actually enable

    My guess is that the floating SPIMISO pin could be picking up noise from the SPIMOSI pin. 

    Is there any other changes around that time?  Any Idea from the time perspective?

    Even if there is some correlation between the FAB and the "failing" vs. not "passing" parts, we are not able to say that the "passing" parts won't eventually fail. With floating pins, there is no way to know what the value will be or what the risk is, since it is dependent on constantly changing environmental factors.

    Since the value of floating pin is not included in the specs, we don't do related test, right? Is there any test data related to floating pin we can share? If no youu may help confirming that we don't have it.

    What I meant by this is that every part goes through the testing process to ensure it complies with the specs from the data sheet, so all we can say is that it complied with the data sheet. Digging up test data & manufacturing data would require looping in other teams from the BU. If you want to go down this route (although I wouldn't recommend it because of my previous answer - it doesn't necessarily tell you anything meaningful), I suggest starting an email chain for this.

    Best Regards,

    Delaney

  • Hi Delaney,

    Let's go this way

    Digging up test data & manufacturing data would require looping in other teams from the BU. If you want to go down this route

    Regards,

    Hang

  • Hi Hang,

    I have looped in the test team on the email thread. I'll close this thread since we will continue via email.

    Best Regards,

    Delaney