Part Number: TMS320F28377S
We’re trying to use Cycle-by-cycle tripping for PWM pulses in the TMS320F28377S chip. The EPWM1 and EPWM2 share the same trip resource, but when the CBC flag is cleared and PWM output resumes, it is observed that the drive signal of EPWM1 has a probability of being blocked for one additional cycle compared to EPWM2, leading to excessive voltage stress.
As shown in the figure below, the pink curve represents the drive signal of EPWM1B. At this time, CMPA of EPWM1 is 0, and the dead-band is enabled so EPWM1B should always remain high. However, while EPWM2A (blue curve) has already ended the CBC blocking and resumed drive output, EPWM1B remains low.
For more information, EPWM1 to 6 are used to control the 12 switching devices of a three-phase T-type three-level inverter. Specifically, EPWM1 and 2 control the four switching devices of leg R, EPWM3 and 4 control leg S, and EPWM5 and 6 control leg T. The correspondence between each EPWM channel and the switching devices of the inverter leg R is illustrated in the figure below.
The specific EPWM channel causing the issue for leg R is not fixed. EPWM1B may block one extra driving cycle compared to 2A, or 2B may block one extra cycle compared to 1A. After multiple rounds of testing, the same behavior has also been observed for EPWM3 and 4. While we have not yet conducted extensive testing on the leg controlled by EPWM5 and 6, we suspect it likely shares the same problem.
During our tests, this phenomenon seems to occur more frequent in EPWM1-2. We attempted to switch the ADC interrupt trigger source to EPWM2 and applied phase compensation to EPWM2-6, which reduced the occurrence probability of the issue. However, the same problem was still captured in subsequent tests.
We want to understand the root cause of this issue and its corresponding solutions. The corresponding configurations of EPWM submodule used in our code are shown below:
EPWM1 serves as the synchronization source, sending a synchronization signal to EPWM2-6 and triggering the ADC sampling interrupt when CTR=0.
EPwm1Regs.ETSEL.bit.SOCAEN = 1;
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;
EPwm1Regs.CMPC = 150;
EPwm1Regs.ETSEL.bit.SOCBEN = 1;
EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTRU_CMPA;
EPwm1Regs.ETSEL.bit.SOCBSELCMP = 1;
EPwm1Regs.ETPS.bit.SOCBPRD = ET_1ST;
EPwm1Regs.ETSEL.bit.INTEN = 1;
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;
EPwm1Regs.ETPS.bit.INTPSSEL = 0;
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;
EPWM1:
Epwm->TBPHS.bit.TBPHS = 0;
Epwm->TBPHS.bit.TBPHSHR = 0;
Epwm->TBCTL.bit.PHSEN = 0;
Epwm->TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPWM2~6:
Epwm->TBPHS.bit.TBPHS = 0;
Epwm->TBPHS.bit.TBPHSHR = 0;
Epwm->TBCTL.bit.PHSEN = 0;
Epwm->TBCTL.bit.SYNCOSEL = SEND_SYNC_IN;
EPWM1 also clears the CBC trip latch when CTR = PRD.
Trip-zone configurations:
Epwm->DCTRIPSEL.bit.DCALCOMPSEL = DC_TRIPIN9;
Epwm->TZDCSEL.bit.DCAEVT2 = TZ_DCAL_HI;
Epwm->DCACTL.bit.EVT2SRCSEL = DC_EVT2;
Epwm->DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;
Epwm->TZSEL.bit.DCAEVT2 = TZ_ENABLE;
Epwm->TZCTL.bit.TZA = TZ_FORCE_LO;
Epwm->TZCTL.bit.DCAEVT2 = TZ_FORCE_LO;
Epwm->DCTRIPSEL.bit.DCBLCOMPSEL = DC_TRIPIN9;
Epwm->TZDCSEL.bit.DCBEVT2 = TZ_DCBL_HI;
Epwm->DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
Epwm->DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;
Epwm->TZSEL.bit.DCBEVT2 = TZ_ENABLE;
Epwm->TZCTL.bit.TZB = TZ_FORCE_LO;
Epwm->TZCTL.bit.DCBEVT2 = TZ_FORCE_LO;
Epwm->TZCLR.bit.CBCPULSE = 1;
Epwm->TZSEL.bit.OSHT1 = TZ_ENABLE;
Epwm->TZCTL.bit.TZA = TZ_FORCE_LO;
