F29H859TU-Q1: How to define a share variable for CPU1, CPU2, CPU3

Shuqing Zhou

Hi team,

I ask this for my customer

My customer want to define a shared global variable to be used by CPU1, CPU2 and CPU3, that means CPU1/CPU2/CPU3 can read and write this variable

In my understanding, all the CPU can access the RAM, although it has different performance

I also notice that for some RAM, some CPU isn't has the program bus

I write a demo: led_ex2_blinky_cpu1_cpu2_cpu3_multi.zip

demo define the variable in LDA RAM

and for CPU1 and CPU2, the variable has the same address, seems it can be read and write by CPU1/CPU2

But for CPU3, it has the different address

Is it exist the shared RAM can be read and written by CPU1, CPU2, CPU3?
If is not, do we have any suggestion that how to customer realize their expecation?

BRs

Shuqing

5 months ago

0 Prarthan Bhatt 5 months ago

TI__Mastermind 18146 points

Hi,

Is the shared variable defined in the CPU3 project also assigned to same memory block as done in CPU1/2 projects ?

You can also use location attribute from c29clang compiler - https://software-dl.ti.com/codegen/docs/c29clang/compiler_tools_user_guide/compiler_manual/c_cpp_language_implementation/attributes/variable_attributes.html#location

<type> symbol __attribute__((location(address)));
 
example - int xyz __attribute__((location(0x30000000))) = 10;

Below is the access and their corresponding wait states, for shared variable you would only need data access from CPU for read/write. Program access means CPU executing code from those memories.

Thanks

0 Shuqing Zhou 5 months ago in reply to Prarthan Bhatt

TI__Expert 3395 points

Hi Prarthan,

Thanks for your reply!

I can define it according to your suggestion, and CPU1/2/3 can read and write it

volatile int shared_var1 __attribute__((location(0x200E0844))) = 0;

volatile int shared_var2 __attribute__((location(0x200E083C))) = 0;

volatile int shared_var3 __attribute__((location(0x200E0840))) = 0;

Is any issue if customer use this way to communicate? Is it need to add some sync scheme to avoid access violation?

BRs

Shuqing

0 Prarthan Bhatt 5 months ago in reply to Shuqing Zhou

TI__Mastermind 18146 points

Hi,

To make sure sequence of read and write is correct, we recommend customers use the IPC module to communicate across cores.

This should work fine.

Thanks

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F29H859TU-Q1: How to define a share variable for CPU1, CPU2, CPU3