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SPI-B master, SPI-A slave test

Monica Zolog
Expert 1905 points


Hi!

I'm trying to test the communication between the 2 SPIs available on Piccolo f28069.

I've configured SPI-B as master and SPI-A as slave. The transmission is on 16bits. The data received by the slave is correct, the problem is the master. It seems I always miss one more shifting. For example, if the slave sends 0x5A5A, the master reads 0x2D2D. The Clock Polarity and Clock Phase are set to 0 for both the master and the slave. I've scoped the SIMO and SOMI and observed that the SOMI outputs the data a bit later than SIMO. But the master is supposed to read the data on the falling edge, right? So, this shouldn't be the problem. Anyway, I've tried to set the Clock polarity of the slave to 1. Now, the master reads the data correct, but the slave misses one shifting. The sendings and readings are done on tx/rx fifo interrupts.

Does anybody have an idea what I'm doing wrong?

Thanks,

Monica

  • 0
    Expert 1905 points

    I've reduced the baud rate, and it seems it works if the baud rate it's <=8.88MHz.

    In the datasheet it's specified that the maximum SPI baud rate is LSPCLK/4, which in my case means 20MHz. The difference is pretty big.

    Does anybody know why is this happening? Can be something else, not just the baud rate?

    Thank you,

    Monica

  • 0 in reply to Monica Zolog
    TI__Prodigy 610 points

    Monica,

    It sounds like your GPIO input qualification may be incorrectly configured.  We recommend using async input (no qualification) for SPI since the SPI peripheral performs synchronization internally.

    From F2806x_Spi.c:

        GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
        GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
        GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
        GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)

    Regards,
    Harrison

  • 0 in reply to HarrisonPham
    Expert 1905 points

    Thanks a lot Harrison!

    I've missed that. I kept reading the SPI doc, and forgot about the others :)

    I did these settings for SPI-B too and test it for 5-bits characters and 16-bits characters. It's working for higher baud rates too. Still, I miss that last shifting for the maximum baud rate (20MHz), but I won't need this speed. Anyway, do you think there can still be something wrong/missing in my settings and that's why it's not working for 20MHz? I've done several tests for the baud rate I need, and it looks good. I hope these were not just 'lucky coincidences'.

    Thanks again,

    Monica

  • 0 in reply to Monica Zolog
    Expert 1905 points

    Hi again!

    I've found this:

    1. The maximum baud rate that can be employed is limited by the maximum speed of the I/O buffers used on the SPI pins. I couldn't find the value...

    2. SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
    LSPCLK = 80MHz.

    3. Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
    Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
    Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.

    So, which is actually the maximum speed?




  • 0 in reply to Monica Zolog
    TI__Prodigy 610 points

    Monica,

    I agree that the timings in the datasheet are a bit confusing.  According to the latest F28069 datasheet, the maximum SPI slave clock frequency is 10MHz for both transmit and receive.

    From page 110 of http://www.ti.com/lit/ds/symlink/tms320f28069.pdf:

    (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
    Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
    Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.

    And for completeness, the F28069 GPIO pads are spec'd up to 20MHz (page 153).

    Regards,
    Harrison