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F29H85X-SDK: Designing an architecture that automatically loads program from Core 1 to Core 2

Alessandro Zani
Prodigy 60 points

Part Number: F29H85X-SDK

Hello,

Our team is attempting to design a software architecture making use of Core 2 of the F29 microcontroller. Our goal is to implement an automatic method for transferring a program from the flash using core 1, then copying it inside the CPU1/2 shared ram (LPA) and subsequently launching automatic execution of code by CPU2 from LPA.

We have taken a look at the examples provided with the f29 SDK but we couldn't find what we were looking for. 

One interesting thread topic is this one: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1497290/f29h85x-som-evm-loading-the-cpu2-and-cpu3?keyMatch=f29h85x%20cpu%20code%20execution&tisearch=universal_search&cf-support=TI%20E2E%E2%84%A2%20design%20support%20forums where a single .out file was generated combining compilation of code for all cores. 

We were wondering how to do so on our own system and is it required to have standalone project each with their own cmd file for each core?

We also attempted to use the multicore led example with separate .out compile outputs for each core but once CPU1 stops at ESTOP0 instruction, we are not able to load the program into CPU2 and 3, getting error due to failing to write PC_FORCE register despite following specified instructions.

 

  • 0
    TI__Intellectual 870 points

    Hi,

    You can take reference from the 'ipc_ex1_basic_cpu1_cpu2_multi' example present in the SDK.

    The CPU2 post build step creates .bin for the CPU2

    The CPU1 pre build step updates the section 'cpu2app' with the size of the CPU2 bin file

    The CPU1 post build steps updates the contents of the section 'cpu2app' with the CPU2 bin file, and this section is loaded to Flash and run from LPA RAM

    We need to load only CPU1.out which loads the CPU2 app section to LPA RAM, when CPU1 core start running, it configures the CPU2 reset vector to LPA RAM and brings it out of reset and CPU2 starts executing from LPA RAM.

    regards,

    Anand