TMS320F28P650SH: F28P65 CMPSS errata: How to implement workaround3?

Hi Masoud,

Thanks for quickly answer!

I talked workaround 3 with customer, but it seem not to do this. Because no ADC channel connect to 3.3V or VERFHI.

About workaround 2, they have use digital filter. Below is their configure:

CTRIPFILCLKCTL = 0x01;

SAMPWIN = 0x3F;

THRESH = 0x3F;

But still will have CMPSS glitch.  Increase CTRIPFILCLKCTL  will help? such as 199, which sampling frequency is 1M.

Best Regards,

Zane

Hi Zane,

The false CMPSS event can be a very short disturbance (up to 50 ns) caused by the ADC S/H cap charge injection on AGPIO-type analog pins when ADC + CMPSS share the same pin. Workaround #2 is to use the CMPSS digital filter with a setting of 50 ns or greater to reject that short disturbance.

When you say we enabled the digital filter but still see glitches, it’s often because the ePWM/XBAR is still using an unfiltered CMPSS output, or the latch/trip path is configured before filtering. So please double-check the routing that If the trip source is tied to an unfiltered output, the filter settings won’t help.

The current delay is already very long.

Best Regards,

Masoud

Hi Masoud,

I can't understand your answer, if I enable digital filter, the signal always enter digital filter then enter ePWM/XBAR.

If workaround2 is not a workaround, why we write it in errata?

Best Regards,

Zane

Hi Zane,

Your shown settings (SAMPWIN=0x3F, THRESH=0x3F) are already strong filtering, so simply changing CTRIPFILCLKCTL to something like 199 just makes the response slower, not more immune to a 50 ns spike. Numbers are already high. That’s why I suspect the filtering is configured incorrectly.

The key detail is that initialization/configuring the CMPSS digital filter is not automatically what every downstream path uses. CMPSS lets you select what drives the trip outputs: async comp, sync comp, filter output, or latched filter output. The ask was to confirm that the drive signal for CTRIPH / CTRIPOUTH is filter output.

Best Regards,

Masoud

Hi Masoud,

I think customer's configure is right. And after increase sampling windows and THERSH, it have some improve, but still have cmpss glitch.

What 50ns refer to ? it is sampling window, if right, how to set THERSH?

Best Reagrds,

Zane

In one hand, thee “50 ns” in the errata is the approximate maximum width of the analog disturbance that can be injected on AGPIO-type analog pins when the ADC S/H capacitor connects/disconnects on a pin that is also being monitored by CMPSS.

On the other hand, the CMPSS digital filter works by sampling the comparator output (SAMPWIN + 1) at a programmable sample clock period and evaluating the number of samples in a window (Effective threshold THRESH + 1). Here the boundary rule is that the THRESH must be <= SAMPWIN. With the customer’s shared settings, SAMPWIN = 0x3F (64 samples) and THRESH = 0x3F (64 samples).

This is essentially the strongest majority filter setting. It requires the input to stay in the new state for 64 samples to switch the filter output.

So if they still see trips, I think one of these are what’s happening: path is not actually using the filtered signal or in the real system, the needed pulse is longer than 50 ns.

Best Regards,

Masoud

Let's actually measure the delay with customer's shared setting:

As you see CMPSS uses SYSCLK (200 MHz):

T_delay = 0x3F * T_s = 0x3F * ((CLKPRESCALE + 1) /200MHz) = 0x3F * (2/200MHz) = 0x3F * 10ns = 640 ns

As I mentioned, this is already longer than 50ns.

Best Regards,

Masoud