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TMS320F2800137: F2800137 SCIC TX interrupt abnormality after enable interrupt nest

Zane Wei
Intellectual 1965 points

Part Number: TMS320F2800137

Hi Team,

I found a very interesting thing that when enable SCIC TX INT nest, even if I turn off SCIC_TX_INT , it still keep entering SCIC TX interrupt function. 

d12cf440-b25e-43ce-bf91-974794d23b86.PNG

 

Could you help run my code in your board and help me find the root case. Thanks!

Project download link:

SCIC_TX issue.zip 

Best Regards,

Zane

  • 0
    TI__Mastermind 25940 points

    Hi Zane, 

    I would not recommend using the Interrupt_disable() function for interrupt nesting, it does many things besides just disabling the PIEIER. With nesting, the sequence needs to be followed in a very specific way. The PIE is likely getting into an unexpected state here. These are the below interrupts I see defined, and this order is how they are automatically prioritized by the PIE. Let me know if any are unused.

    1. ADCC1
    2. TIMER0
    3. EPWM7
    4. SCIA_RX
    5. SCIA_TX
    6. XINT3

    What user-defined priority order are you looking to configure using nesting? I can provide the correct way to implement this. 

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Intellectual 1965 points

    Hi Delaney,

    I found sci_ex2_loopback_interrupts demo is can't understand. We don't put any data in TX FIFO , but it will enter TXISR function after program running. I read TRM, found maybe it maybe related with TXRDY is set after cpu reset, is right? But it will casue TXISR function overrun even if I commented SCI_writeCharArray(SCIA_BASE, sDataA, 2); in sci_ex2_loopback_interrupts TXISR. I can't understand why this happened.

    You can see I commented SCI_writeCharArray, but it always enter TXISR and update sDataA. You can use our demo code have a try.

    Best Regards,

    Zane

  • +1 in reply to Zane Wei
    TI__Mastermind 25940 points

    Hi Zane,

    Is the SCI FIFO enabled? It looks like yes -> If FIFO is enabled, the TXRDY interrupt should immediately fire upon configuring and enabling the SCI module. This is because the TX FIFO interrupt condition is based on having some number of elements empty - so the condition will automatically be met since the TX FIFO is empty to start with. If you clear the interrupt condition inside the ISR but don't write any data to the TX FIFO, the interrupt should fire again since the FIFO condition is still met, and you will get another interrupt. I believe this is what you are seeing?

    The TXRDY interrupt is basically saying: "you can write x number of bytes to the FIFO without overrun - since x slots are empty". If you don't fill up the FIFO in the ISR, the condition will be met over and over again. Applications don't use the TX ISR unless they want pretty much a continuous stream of data. 

    Best Regards,

    Delaney