Part Number: TMS320F28388D
Hi Team,
Posting on behalf of our customer.
I will share this E2E post to our customer so he can reply when needed.
We are contacting you as we are utilising your F28388D MCU for our development.
When it comes to this MCU, our understanding is the following:
- The C28 CPU1 and CPU2 cores are intended to be used as Real-Time compliant "heavy-lifters", i.e. to process any data that is coming through from the CM
- The CM is intended as the "interface with the outside world", as it is the only core that can directly access and use communication interfaces such as Ethernet, EtherCAT, etc.
You have repeatedly stated on your forums that, as of 2025 and now 2026, TI only supports the use of FreeRTOS as the operating system, and lwIP as the TCP/IP stack. Your examples confirm this, with the lwIP example directly compiled for the CM subsystem.
Here lies our problem: the CM subsystem only supports 96KB of usable RAM. FreeRTOS + lwIP on their own take up a considerable portion of this RAM, and there is barely any left over to run application code. Now, while the C28 subsystems support an EMIF to allow expansion of the on-board RAM, the CM subsystem apparently does not.
Is this all correct so far? If so, given that the CM core is the only one that can access the Ethernet peripheral and must use FreeRTOS+lwIP to do so, what is the intended design to make this work with the very small onboard memory? We can currently spin up a few threads and open a few UDP/TCP sockets before we run into FaultISR errors due to insufficient memory.
Regards,
Danilo