• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 82 subscribers
  • Views 179 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

CCS/TMS320F28379D: Using the SDFM to replace SAR ADCs for power electronics applications

TMS320F280039C-Q1: Control Loop Delay when Utilizing SDFM

Neal Malackowski
Prodigy 60 points

Part Number: TMS320F280039C-Q1

Hello, 

For the scenario in the subject line, please consider the following...

  • EPWM_CLKFREQ = 120MHz
  • PWM frequency of 100kHz (Up-Down count mode, 1200 ticks)
  • Control Loop ISR is triggered on a CMPC Up-Count event (CMPC = 600-ISR Latency = 586, 4.88us))
    • Control loop executes and writes a new phase shift value to the PWM shadow register
  • Shadow-to-Active write occurs when counter = zero
  • The controlled parameter is output voltage measured by the SDFM with the following parameters:
    • SINC3 Filter
    • OSR of 64
    • Modulator Clock: 20 MHz
    • Data Rate = 3.2µs
    • Latency = 9.6µs

With the control loop running synchronously with the PWM, and the latency of the SINC3 filter being roughly a switching period, it seems that the control loop will always be calculating the new phase shift based off of old data and the sample-to-output delay time will now become twice the switching period rather just a switching period. Consequently, the phase margin will be reduced and in order to ensure stablity, the bandwidth of the controller will have to be reduced. Ultimately, the tranisent response of the converter will suffer as result of using the SDFM.

Is my understanding of the control theory correct? Is this simply a cost of using the SDFM with that high of an OSR? In order to reduce the delay time and improve the phase margin of the control loop, would I have to reduce the OSR to at most 32 in order for the latency to be less than 4.88us?

Thanks very much,

Neal Malackowski

  • +1
    TI__Expert 7500 points

    Hi Neal,

    Yes, in comparison to SAR ADC, the SDFM data filter latency is considerable delay and can reduce phase margin / achievable bandwidth.

    For a SINC3 data filter, OSR = 64 and fMOD = 20 MHz, data rate is 64 / 20e6 = 3.2 us and latency is equal 3 * 3.2 us = 9.6 us which matches with your math. But it’s not automatically “2 switching periods” of delay and depends on when you sample/read the filtered result and when the PWM update actually takes effect. The total delay is equal SDFM filter latency (say 9.6 us) + PWM update-to-effect delay (time until next load event). With up-down PWM at 100 kHz, PWM udate delay is around 5 us, so you’re in the ballpark of 15 us (1.5*Ts, not necessarily 2*Ts).

    My recommendation for best results is to align the control ISR to the SDFM fresh data moment. You can trigger the control loop from SDFM data-filter-ready, then choose the earliest safe PWM load event (ZERO vs PRD, depending on your scheme) to minimize compute-to-actuate delay.

    Also you can consider reducing SDFM latency by lower OSR or lower order filter based on your noise budget.

    Best Regards,

    Masoud