TMS320F28P650DH: CLB HLC on CPU2

Hi Wynand,
I have just been assigned this thread, I will get back to you in a couple of days.
Thanks,
Praneeth

Hi Praneeth,

Thank you.
I really hope you can help me with this as the project is at an advanced state already.

Best Regards

Wynand

Hi Wynand,
I am looking into it. Meanwhile, can I know why you have added this line?  

HWREGH(PIECTRL_BASE + 0x0B) |=(1<<4);

Thanks
Praneeth

Hi Praneeth,

This line was added as a test for the routing of the IRQ on cpu2.

I wanted to see if the interrupt request from the HLC would trigger my ISR as it is. This line proved that it is triggering the correct ISR and that the interrupts was working on CPU2.
My guess at this point in time is that the problem lies between the HLC and the PIE or possibly between the CLB and the HLC, but I doubt this last one.

Thank you for the help I really appreciate it.

Wynand

Hi Wynand,
I have tested a simple code, in which HLC generates an interrupt. CLB is assigned to CPU2. It worked. 

Remove this line.          HWREGH(PIECTRL_BASE + 0x0B) |=(1<<4);



Please check PIECTRL Registers in Debug view, check if Interrupt 5 in PIEIFR5 is getting set when you run the code. If it is set, then check the same interrupt in PIEIER5. 

Thanks
Praneeth

Hi Praneeth,

Thank you for confirming. I do not see the flag being set in PIEIER5.
As I said when I add the line you want me to remove then the ISR fires as I expect it to be.

Can you please share your configuration code in CPU1 with me so I can see what I am missing.

I have even tried this on the LAUNCHXL board and experience the same behavior as on my board. The different controllers are of course the 659 and 650.

Are you using SysConfig or doe you do a manual setup?

I am also testing a very basic code.

Kind regards

Wynand

Just to add more clarity.
I have been able to run the HLC on CPU1 without any issues and my trouble only came when assigning it to CPU2. So it might be ownership or access control.

The following is a part of my main code on CPU1:

void main(void)
{
    Device_init();

    Device_initGPIO();

    SysCtl_allocateFlashBank(SYSCTL_FLASH_BANK1, SYSCTL_CPUSEL_CPU2);
    SysCtl_allocateFlashBank(SYSCTL_FLASH_BANK4, SYSCTL_CPUSEL_CPU2);
    SysCtl_allocateDxRAM(SYSCTL_D2RAM, SYSCTL_CPUSEL_CPU2);
    SysCtl_allocateDxRAM(SYSCTL_D3RAM, SYSCTL_CPUSEL_CPU2);
    MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS4, MEMCFG_GSRAMCONTROLLER_CPU2);

    Device_bootCPU2(BOOTMODE_BOOT_TO_FLASH_BANK1_SECTOR0);

    Interrupt_initModule();
    Interrupt_initVectorTable();

    SysCtl_selectCPUForPeripheralInstance( SYSCTL_CPUSEL_CLB1, SYSCTL_CPUSEL_CPU2 );
    SysCtl_setPeripheralAccessControl(SYSCTL_ACCESS_CLB1, SYSCTL_ACCESS_CPUX, SYSCTL_ACCESS_FULL);
    SysCtl_selectCPUForPeripheralInstance( SYSCTL_CPUSEL_CLB2, SYSCTL_CPUSEL_CPU2 );
    SysCtl_setPeripheralAccessControl(SYSCTL_ACCESS_CLB2, SYSCTL_ACCESS_CPUX, SYSCTL_ACCESS_FULL);
    SysCtl_selectCPUForPeripheralInstance( SYSCTL_CPUSEL_CLB3, SYSCTL_CPUSEL_CPU2 );
    SysCtl_setPeripheralAccessControl(SYSCTL_ACCESS_CLB3, SYSCTL_ACCESS_CPUX, SYSCTL_ACCESS_FULL);

    Board_init();

Wynand,
I have used SYSCONFIG. 
I have selected CPU2 for CLB1

Checked if Full access is given.

I noticed that PIEIER and IER registers were not enabled, while running the code. Then I added INTERRUPT_init(); function at the end as shown below, then the interrupt workerd.

Apart from this, I did not do anything else. 
Thanks
Praneeth

Hi Praneeth,

Thank you for the response.
To be honest I did not use Device support in SysConfig.
I will give it a try in the new few minutes and see if it resolves my problems.
Thank you for your support.

Sure, if you still face any issue, please let me know

Thank you Praneeth.
I should know by tomorrow whether this is working properly or not.

okay, thanks. Please update if it is working. 

Glad to hear it is working
Thanks
Praneeth