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F29H85X-SOM-EVM: Restarting CPU1 code adfter deploying cpu3 executable

MUKUL CHOUDHURY
Intellectual 550 points
Part Number: F29H85X-SOM-EVM


Hi all,

I needed few clarification regarding TI examples:

I found the following code in led_ex1_blink example for boot from RAM. 

C:/ti/ccs2040/ccs/tools/compiler/ti-cgt-c29_2.0.0.STS/bin/c29objcopy.exe -O binary led_ex1_blinky.out led_ex1_blinky.bin
$(call IF_EQUAL_OPEN, 1, 0) $(PYTHON) C:/ti/f29h85x-sdk_1_02_01_00/tools/boot/signing/mcu_rom_image_gen.py --image-bin led_ex1_blinky.bin --core C29 --swrv 1 --loadaddr 0x200E1000 --sign-key C:/ti/f29h85x-sdk_1_02_01_00/tools/boot/signing/mcu_gpkey.pem --out-image led_ex1_blinky_cert.bin --device f29h85x --boot RAM --img_integ no $(IF_EQUAL_CLOSE)
$(call IF_EQUAL_OPEN, 1, 1) C:/ti/f29h85x-sdk_1_02_01_00/tools/misc/$(UPDATEDUMMYCERT) $(DUMMY_CERT_RAM) led_ex1_blinky.bin $(IF_EQUAL_CLOSE)
$(call IF_EQUAL_OPEN, 1, 1) $(CONCAT) $(DUMMY_CERT_RAM) led_ex1_blinky.bin > led_ex1_blinky_cert.bin $(IF_EQUAL_CLOSE)
  • Why the load address is 0x2010E000?In flash configuration load address was 10001000 which is the code start address.
  • Why do we need to generate the certificate in RAM configuration. Is it not required only for Flash configuration?
  • Even after generating the certificate, there is no post build step to merge it with the executable as was done in CPU1 for flash configuration?

2) I am also trying to run multi core example in CCS in RAM configuration 

led_ex3_blinky_cpu1_cpu3_multi_ra_c29x3.
In this example it is mentioned to deploy first cpu3.out and then cpu1.out
 
If I deploy cpu3.out after cpu1.out, can I execute the program and run it from cpu1 main function?
I see after deploying cpu3.out, the control goes to the cpu3 main function. Is there a function or step that can transfer the control cpu1 main function so that it can boot other cpus.
 
Basically after deploying cpu3.out, I want the program to start from cpu1 main function so that it can boot cpu3.
 
Thanks,
Mukul
 
  • 0
    Intellectual 550 points

    Hi all,

    Any update on this?

    Thanks,

    Mukul

  • 0
    TI__Genius 14966 points
    MUKUL CHOUDHURY said:
    Why the load address is 0x2010E000?In flash configuration load address was 10001000 which is the code start address.

    Where do you see this load addr ?

    The F29 SDK V1.03 multicore CPU1/2/3 LED example has below ram linker cmd file codestart which seems correct to me.

    MUKUL CHOUDHURY said:
    • Why do we need to generate the certificate in RAM configuration. Is it not required only for Flash configuration?
    • Even after generating the certificate, there is no post build step to merge it with the executable as was done in CPU1 for flash configuration?

    In latest SDK example  the post and pre build steps are changed to below , have a look at them.

    MUKUL CHOUDHURY said:

    I am also trying to run multi core example in CCS in RAM configuration 

    led_ex3_blinky_cpu1_cpu3_multi_ra_c29x3.
    In this example it is mentioned to deploy first cpu3.out and then cpu1.out

    Since the SDK example combines all cpu .outs in single CPU1.out there is no need to load other CPU .out individually. Just loading CPU1 .out is sufficient.

    Thanks

  • 0 in reply to Prarthan Bhatt
    Intellectual 550 points

    Hi Prarthan,

    1) I am talking about the command 

    $(PYTHON) C:/ti/f29h85x-sdk_1_02_01_00/tools/boot/signing/mcu_rom_image_gen.py --image-bin led_ex1_blinky.bin --core C29 --swrv 1 --loadaddr 0x200E1000 --sign-key C:/ti/f29h85x-sdk_1_02_01_00/tools/boot/signing/mcu_gpkey.pem --out-image led_ex1_blinky_cert.bin --device f29h85x --boot RAM --img_integ no

    Here load address is 0x200E1000. 

    In the image you shared, code_Start is at SRAM_LPA0 whose origin is 0x20100000 and not 0x200E1000 which is start of SRAM_LDA0.

    The command is present in the following single core example: led_ex1_blink (C:\ti\f29h85x-sdk_1_03_00_00\examples\driverlib\single_core\led\led_ex1_blinky)

    2)  In the example C:\ti\f29h85x-sdk_1_03_00_00\examples\driverlib\multi_core\led\led_ex3_blinky_cpu1_cpu3_multi_ra, multi executable approach is used.

    I don't want to merge the executables for CPU1 and CPU3. I want to use them idependently.

    Thanks,

    Mukul