TMS320F28388D: Reducing operating power consumption of f28388d

Hi Hang,

The TMS320F28388D Connectivity Manager (CM) subsystem can be disabled or have its clock speed reduced through several methods, depending on your application requirements. Here are the recommended approaches:

Method 1: Reduce CM Clock Speed

The Connectivity Manager Clock (CMCLK) speed can be reduced by using the CMCLK divider [1]. The clock itself is derived from PLLSYSCLK or AUXPLLRAWCLK, and you can configure the divider to lower the operating frequency of the entire CM subsystem [1].

Method 2: Disable Individual Peripheral Clocks

Each peripheral clock in the CM subsystem has its own independent clock gating that is controlled by the CMPCLKCRx registers (CMPCLKCR0, CMPCLKCR1, CMPCLKCR2) [1]. These registers are located at the CMSYSCTL base address (0x400F_C000) [2]. By disabling clocks to specific peripherals that are not being used, you can significantly reduce power consumption [3].

Current Reduction by Disabling CM Peripherals

Disabling unused CM peripherals can provide the following typical current reductions [4]:

To disable peripheral clocks, turn off the clock to any unused peripheral using its individual clock-enable bit in the PCLKCRx registers [4].

Method 3: Prevent CM from Booting

The CM subsystem is released from reset by the CPU1 application [5]. If you want to completely prevent the CM system from being active, you can select a boot mode where CM is not supported [6]. According to the boot mode table, the following boot modes only bring up CPU1, leaving the CM system inactive [6]:

• Parallel IO
• SCI / Wait
• CAN
• SPI
• I2C
• USB

By configuring the CPU1TOCMIPCBOOTMODE register to one of these modes, the CM will not execute and remain inactive [5][6].

Implementation Details

The CM subsystem contains a System Configuration block which includes Peripheral Clock Gating functionality, accessible by the M4 core [7]. The relevant clock control registers are:

• CMPCLKCR0-2: CM Peripheral clock gating registers
• CMCLKSTOPREQ0-2: Peripheral Clock Stop Request registers [2]

These registers allow fine-grained control over which parts of the CM subsystem consume power.

Recommendation:

For your application where the CM system is the biggest unused system, the most effective approach would be to prevent the CM from booting by selecting an appropriate boot mode that doesn't initialize the CM (Method 3). If you need the CM for future use but want to minimize power consumption now, use peripheral clock gating (Method 2) to disable all unused CM peripherals and consider reducing the CMCLK divider (Method 1) to lower the overall CM clock speed.

Sources

1. TMS320F2838x Technical Reference Manual - CM Clock Control and Peripheral Clock Gating
2. TMS320F2838x Technical Reference Manual - CMSYSCTL Clock Control Registers
3. TMS320F2838x Technical Reference Manual - CM SYSCTRL Base Address Table
4. TMS320F2838x Data Sheet - Current Consumption Reduction Methods and Peripheral Current Savings
5. TMS320F2838x Data Sheet - CM Boot Process and CPU1TOCMIPCBOOTMODE Register
6. TMS320F2838x Data Sheet - Boot Modes and CPU Support Table
7. TMS320F2838x Data Sheet - CM Subsystem Configuration and Peripheral Clock Gating

Best Regards,

Zackary Fleenor