TBPRDHR on TMS320F28035

I am trying to use the HRPWM on the 28035. It seems to be working OK except that I cannot write to the TBPRDHR register.

I have it configured to give me a 23.72KHz PWM signal with 50% duty cycle. I am getting the correct signal and I can change the period by changing TBPRD, but I see no change when I try to change the TBPRDHR register.

My code to change the TBPRDHR reg is

MEPStepSize = 118

EPwm4Regs.TBPRDHR = MEPStepSize<<8;

I also try to change it with the CCS4 watch window, but it always reads zero.
Can this register be written to and read from via the watch window?

Maybe I have something set wrong or I am misunderstanding how this register works

Any help would be appreciated.

My ultimate goal is to produce a signal with a contstant 50% duty cycle that can be changed from 20 KHz to 28 KHz with as high resolution steps as possible.

HRPWM Initialized code below: 

{

    EALLOW;

    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;  // Disable TBCLKSYNC

      EDIS; 

      EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;            // set Immediate load

      EPwm1Regs.TBPRD = period-1;                             // PWM frequency = 1 / period

      EPwm1Regs.CMPA.half.CMPA = period / 2;              // set duty 50% initially

      EPwm1Regs.CMPA.half.CMPAHR = (0 << 8);              // initialize HRPWM extension

      EPwm1Regs.TBPHS.all = 0;

      EPwm1Regs.TBCTR = 0; 

      EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;

      EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;

      EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;

      EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;

      EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; 

      EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1;

      EPwm1Regs.HRPCTL.bit.HRPE = 1; 

      EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;

      EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

      EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; 

      EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;               // PWM toggle low/high

      EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; 

      EALLOW;

      EPwm1Regs.HRCNFG.all = 0x0;

      EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP;                      //HR MEP control on Falling edge

      EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;

      EPwm1Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD;

      EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;      

      EDIS; 

    EALLOW;

    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;  // Enable TBCLKSYNC

    EDIS;   

    EPwm1Regs.TBCTL.bit.SWFSYNC = 1; 

}