TMS320F28377D: Why can't I use the serial port independently to program TMS320F28377D without the emulator?

Would it be possible to share the bootloader code that runs on CPU2?  The only thing that comes to mind is that CPU2 has not grabbed/gained control of the flash pump semaphore, which would not allow it to erase the flash.

Best,

Matthew

I'm sorry that I can't provide the source code program for CPU2, so I have provided screenshots of some of the functions, hoping this can help you find the problem.

This is the CMD file for CPU2.

This is the main function and initialization part function of CPU2

This is the CPU2 erase flash function

This is the function for CPU2 to read flash data.

In addition, I provided some functions of CPU1 to jump from CPU1 to CPU2.

I'm a bit behind in responding here, I'll take a look at what you provided and reply today.

Best,

Matthew

Okay, I will wait for your reply message.

Can you let me know which source file has the SeizeFlashPump Function?  I can't seem to find this function in our source files.  There should be a corresponding IPC receive command on the CPU1 to give control of the pump to CPU2.

Best,

Matthew

We called SeizeFlashPump function in main. c. Call the ReleaseFlashPump function in the boot_CPU2 function.

Cheng,

Sorry for the lack of reply, I'm going to need some more time on this.  I will reply by the 17th.

Best,
Matthew

I will wait for your message Wishing you a wonderful weekend.

Cheng,

Are you using our example flash kernels in C2000Ware located here: 

C:\ti\c2000\C2000Ware_6_00_00_00\device_support\f2837xd\examples\dual\F2837xD_sci_flash_kernels\

Based on your code I think this is what you are using, but want to make sure.

I see this function in SCI_Boot.c, can you confirm which pins you have connected for the SCI comms?  I want to make sure we are passing the same pins for CPU2 to use in its boot

void Assign_SCIA_IO_CPU2(Uint32 BootMode)
{
    EALLOW;
    DevCfgRegs.CPUSEL5.bit.SCI_A = 1;    //SCIA connected to CPU2
    ClkCfgRegs.CLKSEM.all = 0xA5A50000;  //Allows CPU2 bootrom to take control
                                         //of clock configuration registers
    ClkCfgRegs.LOSPCP.all = 0x0007;

    if((BootMode & 0xF0) == 0x0)
    {
        //
        //OPTION 1
        //
        GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
        GPIO_SetupPinMux(84,GPIO_MUX_CPU2,5);
        GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_ASYNC);
        GPIO_SetupPinMux(85,GPIO_MUX_CPU2,5);
    }
    else
    {
        //
        //OPTION 2
        //
        GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
        GPIO_SetupPinMux(29,GPIO_MUX_CPU2,1);
        GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_ASYNC);
        GPIO_SetupPinMux(28,GPIO_MUX_CPU2,1);
    }
    EDIS;
}

To that end, have you made any modifications to that example code when you ported in for your use case?  

Best,

Matt

Yes, I called the function Assign _SCIA_IOU_CPU2 and made some modifications. The parameter BootMode I passed is 0.

Cheng,

Since we are dealing with JTAG working/standalone not working; I'd like to focus on timing related issues in the code:

This is from SCI_Boot.c in the CPU01 directory line 172.  My changes are encapsulated by //////

 while(IPCLtoRFlagBusy(IPC_FLAG0) | IPCLtoRFlagBusy(IPC_FLAG31)){}

    CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
    DevCfgRegs.SOFTPRES7.bit.SCI_A = 1;
/////////////////////////////////////////////////////////
    DELAY_US(1000);  // Replace the short for-loop
//////////////////////////////////////////////////////
    CpuSysRegs.PCLKCR7.bit.SCI_A = 0;
    DevCfgRegs.SOFTPRES7.bit.SCI_A = 0;
/////////////////////////////////////////////////////////
    DELAY_US(1000);  // Replace the short for-loop
//////////////////////////////////////////////////////

    Assign_SCIA_IO_CPU2(BootMode);
    assignSharedRAMstoCPU2();
/////////////////////////////////////////////////////////
    DELAY_US(10000);  // Replace the short for-loop
//////////////////////////////////////////////////////   
    //
    // CPU1 to CPU2 IPC Boot Mode Register
    //
    IpcRegs.IPCBOOTMODE = C1C2_BROM_BOOTMODE_BOOT_FROM_SCI;

    //
    // CPU1 to CPU2 IPC Command Register
    //
    IpcRegs.IPCSENDCOM = C1C2_BROM_IPC_EXECUTE_BOOTMODE_CMD;

In the F2837xD_sci_flash_kernels_cpu02.c file 

Line 124

    
  ////////////////////////////////////////////////////////
  GPIO_WritePin(31, 1);  // Prove CPU2 is running, you can change the pin based on your PCB
  for(x = 0; x < 100000; x++){}
  GPIO_WritePin(31, 0);
/////////////////////////////////////////////////////////  
    Uint16 x = 0;
    for(x = 0; x < 32676; x++){}
    for(x = 0; x < 32676; x++){}

    IpcRegs.IPCBOOTSTS = C2_BOOTROM_BOOTSTS_SYSTEM_READY;
    while(IpcRegs.IPCBOOTMODE != C1C2_BROM_BOOTMODE_BOOT_FROM_SCI){}

    EINT; //enable global interrupt INTM
    ERTM; //enable global realtime interrupt

And then at line 140, let's re-init the SCI to make sure this didn't get corrupted

SeizeFlashPump();
    Init_Flash_Sectors();
    //put GetFunction here
///////////////////////////////////////////    
    SCIA_Init(SCI_BOOT);  // ADD THIS LINE
//////////////////////////////////////////    
    uint32_t EntryAddr = SCI_GetFunction();

//
// Leave control over flash pump
//
    SignalCPU1();
    return EntryAddr; //load entry address of application into
                      //RPC: return program counter
}

Best,
Matthew

You will also need to add these prototypes:

extern void SCIA_Init(Uint32 BootMode);
extern void GPIO_WritePin(Uint32 pin, Uint32 outVal); to the cpu02.c file

Let's see if extending some of these timings gets things to work in standalone mode.

I have successfully found a solution, which is to block the code in the following image. When I keep this part of the program, it will crash here. After blocking this part of the code, the internal flash erase, read and write functions can be used normally through SCI. I think you can tell me the reason for this problem, thank you for that.