F28377D-SEP: McBSP does not generate XINT when XRDY is changed from 0 to 1

Hidehiko Kaya

Intellectual 700 points

Part Number: F28377D-SEP
Other Parts Discussed in Thread: C2000WARE

Hi experts,

I use McBSP as SPI.

However CPU does not receive an interrupt from McBSP

when McbspaRegs.SPCR2.bit.XRDY is changed from 0 to 1.

Could you let me know how do I get a sample program ?

Best regards,

Hidehiko

2 months ago

0 MatthewPate 2 months ago

TI__Guru* 83860 points

Hidehiko,

Thanks for reaching out to the E2E. If you could please give me another day to look into your question a bit more to see if I can locate some example code for what you are trying to do.

Thanks,
Matthew

+1 MatthewPate 2 months ago in reply to MatthewPate

TI__Guru* 83860 points

Hidehiko,

There is an interrupt example for McBSP in C2000Ware here C:\ti\c2000\C2000Ware_6_00_00_00\driverlib\f2837xd\examples\cpu1\mcbsp\mcbsp_ex3_loopback_interrupts

https://dev.ti.com/tirex/explore/node?isTheia=false&node=A__AOIEjA-KCJ.6u9paOdNi7A__c2000ware_F2837xD_module_software_package__1kRFgrO__LATEST

This is not in SPI mode, but you can use the ISR setup in the same way. For your case XINTM bit in SPCR2 register should be left at "0" to trigger when the FIFO is ready for new data.

Best,

Matthew

C2000™︎ microcontrollers

C2000 microcontrollers forum

F28377D-SEP: McBSP does not generate XINT when XRDY is changed from 0 to 1