TMS320F28377D: EPWM miss pulse issue, with fixed phase shift period

Hi Hang,

Let me try this.

The issue occurs due to the interaction between the TBCTR value and CMPA when they are very close or equal. Here's what happens:

1. When a sync event occurs, the TBCTR is loaded with the TBPHS value
2. If CMPA happens to be equal to or very close to TBPHS, the counter can "jump" past the compare point during the sync event
3. This causes the expected compare event (and corresponding output transition) to be missed

While TBCTR values should maintain their phase relationship after initial sync, there are specific scenarios where the hardware behavior causes issues:

• When TBPHS is loaded at the sync point, the hardware prioritizes this action
• If CMPA = TBPHS (or very close), the compare logic might not have sufficient time to detect the match condition during this transition
• The counter effectively "jumps" from its current value to TBPHS, potentially skipping the CMPA value

1. Shadow Registers and Load Events: Ensure CMPA updates occur at zero/period (CTRMODE=UPDOWN) to prevent changes during critical timing points

2. Add a Small Offset: Modify your algorithm to prevent CMPA from ever being exactly equal to TBPHS values:

3. Sync Timing Adjustment: Configure sync to occur at a point in the cycle far from where compare events are expected

4. Use Time-Base Clock Prescaler: A higher TBCLK division factor can help reduce timing sensitivity

Let me know if any of these works.

Thanks

Srikanth

Srikanth,

Thanks for helping me understanding the problems here, I'd like to confirm if I've understood you correctly with the following examples:

PRD=6 CMPA=3, TBPHS(ePWM2)=3, sync to count up, updown count, the counter should goes as the following:

ePWM1: [2 1 0(sync) 1 2]

ePWM2: [1 2 3(sync) 4 5]

When ePWM2 TBCTR = 3, the sync event and CAU event occurred at the same time. 

Srikanth Yerra said:

If CMPA = TBPHS (or very close), the compare logic might not have sufficient time to detect the match condition during this transition

Do you mean in this case the CAU would be skipped in this case? Since the CTR is already holds 3 before the sync, and remains 3 throughout the entire cycle, which is the same as a regular countering cycle. why might the compare logic not have enough time to detect the event?

If my understanding is incorrect, could you give me an example like the above?

Let's assume that we've ensured ePWM shadow to active only on CTR=ZERO, and the phase of ePWM1 and ePWM2 have been synced after the first cycle, TBPRED are and TBPHS are fixed, and CMPA may varies, could you illustrate how the CAU can be missed in the next cycles?

Regards,

Hang

Hi Hang,

Let me take a step back.

It make sense what you have explained in your initial question. Since your ePWM2 TBCTR is skipping  2 which is the CMPA value, it's possible to see the pulse skip. And it should happen only at you first sync.

Hang Yang said:

If we can ensure TBCTR would not skip, then cause of miss pulse might be a CMPA change. However, with the CMPA only load on CTR=0 (and not load a sync), I can see no ways that the CTR can missing CMPA.

May I know which ePWM CTR=0 are you mentioning? I think the sync is happening at TBCTR=0 of ePWM1. Could you please elaborate your concern here

Thanks

Srikanth

Hi Srikanth,

Srikanth Yerra said:

which ePWM CTR=0 are you mentioning?

I am referring to the CTR=0 of each ePWM. For all pwm, the shadow to active only happens upon its own CTR=0 event, but not a sync event. Of course, for ePWM1, the sync event will happen at the CTR=0 as well.

That said, my doubt is that looks like if we ensure shadow to active only at CTR=0, prd and phs is constant and exclude the first cycle, looks like there is no way the CTR can skip CMPA. In this case, the theory cannot explain the missing pulse we are seeing.

Regards,

Hang

Hi Hang,

To better assist could you share a pictorial description of your configuration and the scope results of skipped PWM waveforms.

Thanks

Srikanth