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TMS320F28P650DH: PWM DC blanking seems to be uneffective

T Z
Prodigy 10 points

Part Number: TMS320F28P650DH
Other Parts Discussed in Thread: C2000WARE, PMP41081

Hello TI expert:

CH1(Yelow)/CH2(Green) is the PWM1A/PWM1B from the AQ submodule through CLB output Xbar. Both of them go high at CTR=ZRO configured in AQCTLA/AQCTLB as shown below. By the way, count-up mode is used and TBPRD is configured as 200k under100MHz PWM clk.

CH4(red) is the latched CMPSSx output, which will trip PWM1A to low when it is high through DC submodule. However, there is a 2us blank window starts from CTR=zero and also a sync pulse to reset the cmpss latch at CTR=ZRO.

So, PWM1A is expected to be a 2us/200khz pulse.

But as you can see from the picture below, the PWM1A is tripped unexpectly when the CMPSS output is high near CTR=ZRO.  

So, what is the problem? How should I do?

Thanks.

 

  • 0
    TI__Mastermind 18696 points

    Hi,

    T Z said:
    Both of them go high at CTR=ZRO configured in AQCTLA/AQCTLB as shown below

    What are your epwm configurations, I could not find them in the question posted.

    T Z said:
    AQ submodule through CLB output Xbar

    Why are you using CLB o/p XBAR ?

    Could you try to refer to epwm_ex5_digital_compare_event_filter in C2000ware to understand how DC blanking window works.

    Thanks

  • 0 in reply to Prarthan Bhatt
    Prodigy 10 points

    Hi, Prarthan

    Sorry for the delay due to out-of-office. The whole background is HHC control validation<spradj1a.pdf>.

    What are your epwm configurations,

    Pls reference to the user guide, spradj1a.pdf for detailed PWM configurations of PWM1A: Set at CTR=ZRO, Clear at T1 EVENT<CH4(red)/CMPSS output is high>.

    Figure 2-3. Block Diagram of the System Control Logic Within C2000 in Digital Control Implementation for Hybrid Hysteretic Control LLC Converter (Rev. A)\

    According to the document, PWM1A width is between the Tmax(TBPRD) and Tmin(CMPSS blank window).

    However, a pulse(CH1) is observed as shown in the picture for PWM1A while the on time is expected to be Tmax.  Please help check the problem.

    Why are you using CLB o/p XBAR ?

    To explore the problem, PWM1B is added and sensed from OUTPUT XBAR pin.   PWM1B configuration: Set at CTR=ZRO and Clear at 2us through CMPB compare event.

    Thanks very much.

  • 0 in reply to T Z
    TI__Mastermind 18696 points

     Transferring this thread internally to the app note author to better help you

    Thanks

  • 0 in reply to Prarthan Bhatt
    Prodigy 10 points

    Thanks for your help.

  • 0 in reply to T Z
    TI__Mastermind 23441 points

    Hi,

    Are you working with a custom HHC LLC design or have you directly reproduced our PMP41081 hardware? I recall testing this design around the 120kHZ range. Have you directly adjusted the switching frequencies? If so, you would also need to adjust the AQ/CMP associated with the minimum frequency clamping. For the maximum frequency clamping, you would need to ensure that the PWMXBAR and DC connection are properly configured in both CMPSS and EPWM modules

    Regards,

    Peter

  • 0 in reply to Peter Luong
    Prodigy 10 points

    Hi, Peter

    Thanks for your help. We directly reproduce your PMP41081 control method with our hardware.

    I think we can simplify the issue.  It happens only at a very special scenario:  

    But as you can see from the picture, the Master drive(PWM1A) is tripped unexpectedly when the rising edge of CMPSS output(T1 event) is very close(i.e. 3-5 PWM clock) to the next period(CTR=ZRO).

    If anyone can simulation this situation, I think the problem will be very clear.

    It is a boundary problem: It looks like T1 event is recognized at CTR=0(Marks for the new period).

    Our design works fine if the problem doesn't happen. So you can consider the logic error during copy later.

    Best regards!

  • 0 in reply to T Z
    TI__Mastermind 23441 points

    Hi,

    Understand your issue. It looks like you are using F28P65x but original software is for F28003x device, so some software adjustments have been made to support the newer device. Can you help to confirm the blanking mode is correctly configured? As well, I see that you are using 100 MHz EPWM clock which is actually reduced from the F28003x 120MHz EPWM clock. Can you try changing to leverage the 200 MHz EPWM clock by changing the divider? I wonder if the lower clock also may have an impact on this issue. If you provide your configuration directly, I can further review

    Regards,

    Peter