TMS320F28P650DK: Issue Uploading To Custom F28P65 Board

Hello,

Apologies for the delay, yesterday was a holiday in the US. Please expect a reply by the EoD.

Best,
Matt

Hello,

Can you share your clock configuration settings? Are you using an internal or external oscillator? If using an external oscillator, does the issue happen when using the internal oscillator (i.e. INTOSC2)?

Best,
Matt

HI,

We have an external oscillator on our board, and we have tried to boot with both the internal and external oscillator. When the device support module is used, we get the error "no compatible debug core found" in both cases. With the device support module disabled, the program fails at ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); with both configurations. 

Here is the generated file from the clock tree file itself:

#ifndef CLOCKTREE_H
#define CLOCKTREE_H

//*****************************************************************************
//
// Summary of SYSPLL related clock configuration
//
//*****************************************************************************
//
// Input Clock to SYSPLL (OSCCLK)	= 10 MHz    (INTOSC1 provides OSCCLK)
//
//##### SYSPLL ENABLED #####
//
// PLLRAWCLK				= 160 MHz   (Output of SYSPLL if enabled) 
// PLLSYSCLK				= 160 MHz
// CPU1CLK					= 160 MHz
// CPU2CLK					= 160 MHz 
// CPU1_SYSCLK				= 160 MHz
// CPU2_SYSCLK 				= 160 MHz
// LSPCLK					= 40 MHz 
// EPWMCLK 					= 160 MHz	
	
//*****************************************************************************
//
// Macro definitions used in device.c (SYSPLL / LSPCLK)
//
//*****************************************************************************
//
//	Input Clock to SYSPLL (OSCCLK) = INTOSC1 = 10 MHz
//
#define DEVICE_OSCSRC_FREQ          10000000U
//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// SYSPLL ENABLED
// SYSCLK = 160 MHz = 10 MHz (OSCCLK) * 32 (IMULT) / (1 (REFDIV) * 2 (ODIV) * 1 (SYSCLKDIVSEL))
//
#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_OSC1  | SYSCTL_IMULT(32) | \
									 SYSCTL_REFDIV(1) | SYSCTL_ODIV(2) | \
									 SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
									 SYSCTL_DCC_BASE_0)
									 
									 
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 32) / (1 * 2 * 1))

//
// Define to pass to SysCtl_setLowSpeedClock().
// Low Speed Clock (LSPCLK) = 160 MHz / 4 = 40 MHz
//
#define DEVICE_LSPCLK_CFG  			SYSCTL_LSPCLK_PRESCALE_4

#define DEVICE_LSPCLK_FREQ          (DEVICE_SYSCLK_FREQ / 4)

//*****************************************************************************
//
// Summary of AUXPLL related clock configuration
//
//*****************************************************************************
//
// Input Clock to AUXOSCCLK	= 25 MHz (X1 provides AUXOSCCLK)  
//
//##### AUXPLL ENABLED #####
//
// AUXPLLRAWCLK				= 125 MHz (Output of AUXPLL if enabled)
// AUXPLLCLK				= 125 MHz 
//
//*****************************************************************************
//
// Macro definitions used in device.c (AUXPLL)
//
//*****************************************************************************
//
//	Input Clock to AUXPLL (AUXOSCCLK) = X1 = 25 MHz
//
#define DEVICE_AUXOSCSRC_FREQ 		25000000U
//
// Define to pass to SysCtl_setAuxClock(). Will configure the clock as follows:
// AUXPLL ENABLED
// AUXPLLCLK = 125 MHz = 25 MHz (AUXOSCCLK) * 40 (IMULT) / (2 (REFDIV) * 4 (ODIV) * 1 (AUXCLKDIVSEL))
#define DEVICE_AUXCLK_FREQ          (DEVICE_AUXOSCSRC_FREQ * 40) / (2 * 4 * 1)
//
#define DEVICE_AUXSETCLOCK_CFG      (SYSCTL_AUXPLL_OSCSRC_XTAL_SE  | SYSCTL_AUXPLL_IMULT(40) | \
									 SYSCTL_REFDIV(2) | SYSCTL_ODIV(4)| \
									 SYSCTL_AUXPLL_DIV_1 | SYSCTL_AUXPLL_ENABLE | \
									 SYSCTL_DCC_BASE_0)
									 
									 

	
//*****************************************************************************
//
// CPU1CLK / CPU2CLK Domain (160 MHz)
//
//*****************************************************************************
// VCRC
// TMU
// FPU
// HWBIST
//	

//*****************************************************************************
//
// CPU1 SYSCLK Domain (160 MHz)
//
//*****************************************************************************
// DCC
// DCSM
// CPUTIMERx
// DMA
// CLAROM
// CLA1
// XINT
// PIE
// GSxRAMs
// LSxRAMs
// MSGRAMs
// Mx/DxRAM
// BootROM
// ERAD
// WD
//	

/////////////////////	
// Gated CPU1 SYSCLK
/////////////////////
// USB
//

//*****************************************************************************
//
// CPU2 SYSCLK Domain (160 MHz)
//
//*****************************************************************************
// BootROM
// DCSM
// GSxRAMs
// WD
// CPUTIMERx
// DMA
// CLA1
// XINT
// PIE
// LSxRAMs
// MSGRAMs
// Mx/DxRAM
// ERAD
//
	
/////////////////////	
// Gated CPU2 SYSCLK
/////////////////////
// CPU2_CLA1
// CPU2_Timer
//
//*****************************************************************************
//
// Gated Peripheral EPWM Domain (160 MHz) 
//
//*****************************************************************************
// EPWM
// HRPWM
//
//*****************************************************************************
//
// Gated Peripheral SYSCLK Domain (160 MHz) 
//
//*****************************************************************************
// ADC
// CMPSS
// DAC
// ePWM
// eCAP
// eQEP
// I2C
// AES
// SDFM
// FSI
// PMBUS
// BGCRC
// SPI
// SCI
// EPG
// CAN
// UART
// LIN
// MCAN
//	
//*****************************************************************************
//
// Gated LSPCLK Domain (40 MHz) 
//
//*****************************************************************************
// SCI
// SPI

#endif // CLOCKTREE_H

Hello,

Which version of SysConfig are you using?

Liong Ma said:

We are programming the P65 with a JTAG connected to the XDS110 of the LAUNCHXL-F28P65X on CCS, with the 0-Ohm resistors removed from the LAUNCHXL

To confirm, all of these resistors were depopulated?

Liong Ma said:

Additionally, when enabling the device support module to use the clock tree tool, we are unable to upload to the board, as we get the error message, "No compatible debug core found." with no additional information.

Can you try connecting with through "Project-less Debug" and then load the firmware? Please ensure the correct P65x variant is selected in the target configuration file (.ccxml). Details can be found here: https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_debug-main.html#manual-launch

Liong Ma said:

the program fails at ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); with both configurations. 

Can you use the flash tool to verify that the program is correctly installed? In CCS: Run > Load > Verify Program...

Best,
Matt