F29H850TU: Maximum delay for EPWM_ICL

Hi, 

I apologize as the expert is currently OoO. Please expect a reply when they return next week. 

Kind regards,
AJ Favela 

Hello Allison,

Thank you for your reply.

However it is not related to MINDB. 
As checked just in case, the MINDBDLY register is 0, so it is not considered to be a delay derived from MINDB.

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EPWM1-A, EPWM2-A delay when using ICL-XBAR:

EPWM1-a, B, EPWM2-a, B Delay when all ICL-XBAR passes
Outputs EPWM2-a, B with the same settings
Set ICL so that EPWM1-a = EPWM2-A.
Output MINDB of EPWM2-B via ICL-XBAR (DB is not set, ICL is set)
→ EPWM1-a (ICL) is 1.8ns delay for EPWM2-B (ICL)

Outputs EPWM1-a, B with the same settings
Set ICL so that EPWM2-a = EPWM1-A.
Output MINDB of EPWM1-B via ICL-XBAR (DB is not set, ICL is set)
→ EPWM2-a (ICL) delay of 0.2 ns to EPWM1-B (ICL)

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Synchronization delay due to EPWMSync:
EPWM1 and EPWM2 are synchronized, but changing the value with setPhaseShift did not change the delay value.
Therefore, we do not believe that this is due to synchronization delay

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Also just for reference, this thread is related to this E2E (https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000-microcontrollers---internal/f/c2000-microcontrollers---internal-forum/1618509/f29h850tu-regarding-epwm_icl-delay.)

So we would like to understand what is the maximum delay that can be expected here. Could you please tell what is the maximum delay for EPWM_ICL?

Hello, Allison is out of office today.  You can expect her reply early next week.

Hi Bhavpreeta,

Thanks for the patience. I see Prarthan was also helping with your query before on the other thread. Let me sync with him on any action he had already taken here as well. 
Best Regards,

Allison Nguyen