Part Number: TMS320F28379D
static void SPIB_DEV_GPIO_Init(void)
{
/* MOSI */
GPIO_setPinConfig(GPIO_63_SPISIMOB);
GPIO_setPadConfig(63, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(63, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(63, GPIO_DIR_MODE_IN);
/* MISO */
GPIO_setPinConfig(GPIO_64_SPISOMIB);
GPIO_setPadConfig(64, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(64, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(64, GPIO_DIR_MODE_OUT);
/* SCLK */
GPIO_setPinConfig(GPIO_65_SPICLKB);
GPIO_setPadConfig(65, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(65, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(65, GPIO_DIR_MODE_IN);
/* CS — HARDWARE SPISTE (CRITICAL) */
GPIO_setPinConfig(GPIO_66_SPISTEB);
GPIO_setDirectionMode(66, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(66, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(66, GPIO_QUAL_ASYNC);
}
//void SPIB_InitTx(void)
//{
// int i;
// for(i=0;i<8;i++)
// {
// SPI_writeDataNonBlocking(SPIB_BASE, txBuffer[i]);
// }
//}
void SPIB_DEV_Init(void)
{
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB);
SPIB_DEV_GPIO_Init();
SPI_disableModule(SPIB_BASE);
SPI_setConfig(SPIB_BASE,
DEVICE_LSPCLK_FREQ,
SPI_PROT_POL0PHA0, // MUST match Zynq spidev
SPI_MODE_PERIPHERAL,
0, // ignored in slave
8); // spidev default
SPI_enableFIFO(SPIB_BASE);
SPI_disableLoopback(SPIB_BASE);
SPI_setEmulationMode(SPIB_BASE, SPI_EMULATION_FREE_RUN);
SPI_clearInterruptStatus(SPIB_BASE,
SPI_INT_RXFF | SPI_INT_RX_OVERRUN);
//
// SPI_setFIFOInterruptLevel(SPIB_BASE,
// SPI_FIFO_TX0,
// SPI_FIFO_RX1); // RX interrupt on 1 byte
// SPI_enableInterrupt(SPIB_BASE,
// SPI_INT_RXFF | SPI_INT_RX_OVERRUN);
// SPI_disableInterrupt(SPIB_BASE,
// SPI_INT_RXFF | SPI_INT_RX_OVERRUN);
/* Preload FIRST byte so first clock doesn't send garbage */
// SPI_writeDataNonBlocking(SPIB_BASE, txdata);
//SPIB_InitTx();
SPI_resetTxFIFO(SPIB_BASE);
SPI_resetRxFIFO(SPIB_BASE);
SPI_writeDataNonBlocking(SPIB_BASE, txdata);
txIndex = 1;
SPI_enableModule(SPIB_BASE);
}
void SPIB_Poll(void)
{
uint8_t rxData;
// uint8_t txdata = 0x22;
/* Check if master sent 1 byte */
if (SPI_getRxFIFOStatus(SPIB_BASE) >= SPI_FIFO_RX1)
{
uint8_t rxData = (uint8_t)(SPI_readDataNonBlocking(SPIB_BASE) & 0xFF);
// uart_printf(" \r\n");
uart_printf("slave received: 0x%02X\r\n", rxData);
// uart_printf("===========================\r\n");
/* Prepare response */
uint8_t response = rxData + 1; // example logic
/* Wait until TX FIFO has space */
while (SPI_getTxFIFOStatus(SPIB_BASE) == SPI_FIFO_TXFULL);
/* Load response BEFORE next master clock */
SPI_writeDataNonBlocking(SPIB_BASE,response);
uart_printf("slave response: 0x%02X\r\n",response);
}
/* Handle Overrun */
if (SPI_getInterruptStatus(SPIB_BASE) & SPI_INT_RX_OVERRUN)
{
uart_printf("SPI RX OVERRUN!\r\n");
SPI_resetRxFIFO(SPIB_BASE);
SPI_resetTxFIFO(SPIB_BASE);
SPI_clearInterruptStatus(SPIB_BASE, SPI_INT_RX_OVERRUN);
}
}
I am checking the SPI communication between the Processor and the Controller, where the Processor acts as the Master and the Controller acts as the Slave. The MOSI communication from the Processor to the Controller is working correctly, and the Controller is receiving the data. However, the Processor is not receiving data through the MISO line.
I probed and verified that data is being transmitted from the controller’s MISO line. However, the transmitted data is always zero. I also tried modifying the logic to send back the received data plus one, and even attempted sending hardcoded data, but the issue still persists.
Any suggestion to resolve this issue.