Thorben,

If you want to just update CMPAHR/CMPBHR only and not the TBPRDHR, there is a cleaner way to do this using Global Load Support feature of Type 4 ePWM module in F28003x device. You can refer to section 20.4.7 Global Load and section 20.5.3 Operational Highlights for the Counter-Compare Submodule of TRM.

You can update all shadow load registers and then engage the latch by using EPWM_setGlobalLoadOneShotLatch(myEPWM1_BASE); or HRPWM_setGlobalLoadOneShotLatch(myEPWM1_BASE); to indicate that all shadow has been updated and transfer shadow to active on next update event (zero/period/both).

You can refer to the example 14 of C2000WARE as follows to see use case and required configuration:

Let me know if any questions.

If it is okay for you, may I know what application/topology is this? Based on that I can provide you optimized recommendation to do this.

Regards,

Sumit

Thorben,

1. When in shadow load, when the LOADAMODE/LOADBMODE is set to Freeze, it will halt all the transfer from shadow to active register till you select other modes. Since its shadow load mode, CMPA register set as shadow register so you will still see that this register is being written in expression window but it will not transfer this value to backend active register which is not visible in expression window. 

After the freeze mode activated, actual PWM waveform it should retain its earlier duty value. Are you observing this duty change in scope? Because 

2. This recommendation is only applied in case where you are simultaneously updating TBPRDHR with CMPAHR/CMPBHR. This is specific case for resonant converter applications where both period and duty need to be updated every ISR. When it does it may cause 1~2 TBCLK jitter. But if you are only doing duty update using CMPAHR/CMPBHR then you should be fine with this feature.

3. Since you are using HR mode, you will need select load mode either at "Load on either CTR = Zero or CTR = PRD". In the mechanism that I explained latch is not engaged till you invoke that one shot latch using the API specified above. Even after latch enable, it will only transfer from shadow to active specified by load mode (i.e.  "Load on either CTR = Zero or CTR = PRD"). This just makes sure that you are done writing shadow register before this shadow to active transfer happens. This is useful especially when there are multiple ePWM need to be updated, because if you use freeze mechanism its still sequential process versus one shot in which all transfer happens at the same instance after master ePWM latch is engaged. You can refer the example that I specified.

Let me know if this makes sense. 

Regards,

Sumit

Hallo Sumit,

To 1. What you describe is what I would expected from the TRM, but I observe the very opposite in the scope. I measured the duty-cycle at the GPIO-Pin and the duty-cycle changes even though I configured the shadow load to be frozen. It seems to be even worse: It seems, that in freeze mode, instead of writing the shadow registers, the values are directly written into the active registers. Thus, from what I see on the scope, the load of the new values seem to happen even between CTR = Zero or CTR = PRD.

Thanks for the clarification in 2. and 3. Even though I will try out these method, I still wonder, why this freezing mechanism does not work.

Kind Regards

Thorben,

On 1, I tried both using CPU and manually writing these freeze bit in expression window and I see no change in duty on my scope. When I revert this setting I was able to see new duty updated. Do you see the same in your register window? Also, when you write using CLA do you see following register updated?

on 2/3 thanks for trying out this feature let me know if any issue.

Regards,

Sumit

In the fist step, the LOADxMODE Registers are set to 0b11 (via setting CMPTRL = 0x000F) resulting in the following set of registers:

And in this case, if I update the cmp-registers (CMPA/CMPB), immediately, the duty cycle changes and the registers change as follows:

If I, in the next step, free the shadow registers, CMPCTL change as follows, but this has no noticeable effect to the duty cycle. 

 (the same applies for 0x0005 instead of 0x000A)

I see when you when you update CMPA/B register, SHDWBFULL/SHDWBFULL flag/bit get status high. For me its was showing low indicating CMPA/B register are not full and can be written. Seems there is abnormal CMPA/B writing operation happening.

I would like to suggest you try this same operation with CPU or manual writing directly to the register than CLA to determine if CLA writing is abnormal or not.

Regards,

Sumit

We tried out all: Setting the registers via

- Registers in Expressions view

- Register in Registers view

- via CPU

- via CLA

It all resulted in the same behavior (as described above).

Are there any side effects from other peripheral settings or any limitations for using this freezing feature? 

Regards, 

Thorben

Strange! I can't think of side effect due to other peripheral. I don't see freeze will do that.

One thing you can cross check if you have configured ePWM in shadow load mode or immediate load mode properly or not. Note in register description says that freeze is ineffective when in immediate mode and it works only in shadow load mode.

You also can cross verify these findings by using any ePWM/HRPWM example from C2000ware. e.g. ePWM example 13 to test this functionality and trace it back to your code to see what could be causing this.

Meanwhile, you can try the one shot global load mechanism to see if that serves the purpose.

Regards,

Sumit