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TMS320F28375S: Setup and Hold specs for GPIO synchronization and the eQEP module

Zachary Baltzer
Prodigy 30 points

Part Number: TMS320F28375S

I'm working on a project with the TMS320F28375SZWTT where we're using GPIO104, Pin J2, EQEP3A to count pulses from an external high speed device. I understand that the max input frequency for the eQEP module, in theory, is SYSCLK/2, however, there must be some setup and hold requirement for the sysclk qualification that would reduce the max frequency a bit? What is the worst case setup and hold we would see on the pins which would allow us to calculate the realistic lower bound for eQEP Fmax?

  • 0
    TI__Intellectual 990 points

    Hi,

    The frequency of the signal that can be applied at the inputs of eQEP depend on the sampling period and pulse width duration. In the case of a GPIO input pin, the input qualification can be specified as only synchronized to SYSCLKOUT or qualification by a sampling window. For case when input is synchronized to SYSCLK, a SYSCLKOUT period of delay is needed for the input to the device to be changed.

    Also, the QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).

    You can refer Section 7.4 of Technical Reference Manual (TMS320F2837xS Real-Time Microcontrollers Technical Reference Manual (Rev. I)) and  section 6.9.8.2 GPIO - Input Timing in datasheet (TMS320F2837xS Real-Time Microcontrollers datasheet (Rev. K) for more details.

    Thanks,

    Divesh

  • 0 in reply to Divesh Dang 18431815
    TI__Intellectual 990 points

    Hi, 

    You can refer to section 6.11.3.1 eQEP Electrical Data and Timing in TMS320F2837xS Real-Time Microcontrollers datasheet (Rev. K).

    Thanks,

    Divesh

  • 0 in reply to Divesh Dang 18431815
    Prodigy 30 points

    I understand this, as well as your comment above - this does not answer the question I asked. 

    The sampling period is 1 SYSCLK, yes, if QUALPRD = 00. That's exactly why I'm asking this question.

    Imagine the qualification happens on the rising edge of SYSCLK. Now, imagine the input signal to a GPIO is exactly SYSCLK/2, and "phase" of 0, where the rising edge of the input signal exactly matches a rising edge of SYSCLK. According to the spec, as far as I can tell, this meets the minimum requirements for the eQEP block, however EE fundamentals tell me that cannot be a valid condition. All clocked logic circuits have some sort of setup and hold spec that must be met.

    Now, taking the phase=0 case, this means that the input signal must be a bit longer than SYSCLK/2, as it needs to come up a bit before the first rising edge, and needs to stay a bit longer after the second rising. My question is, what is the setup and hold time for the GPIO qualification block in the QUALPRD=00 case?

  • 0 in reply to Zachary Baltzer
    TI__Expert 6130 points

    Zachary,

    Good question, I can understand the interpretation you made.  The implementation is a little different.

    For the QUALPRD=00 case, the synchronizer actually only looks at one edge of clock.  So, the actual minimum is 1*sysclk+(small su/h margin).  We have rounded this up in the datasheet to 2*sysclk.

    I definitely can see why you interpreted 2*sysclk as inferring two clock edges being sampled, but hope this explains it sufficiently.

    Best regards,
    Jason