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TMS320F28377D: VDD Requirement

Hideaki Matsumoto
Genius 9765 points

Part Number: TMS320F28377D

Hi,

We've received some inquiries about VDD requirement from my customers.

Could you help to answer their questions below ?

 

There is the description in the datasheet of F28377D.

6.9.1.3 VDD Requirements

The internal VREG is not supported. The VREGENZ pin must be tied to VDDIO and an external source used to supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO.

VDDOSC and VDD must be powered on and off at the same time. VDDOSC should not be powered on when VDD is off. For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata.

 

Could you explain "VDDOSC and VDD must be powered on and off at the same time." in more detail ?

Does it mean that the ramp up point circled in blue is the same between VDDOSC and VDD ?

Is there any problem in the following power sequence ?

ramp up.jpg

 

 

How about power off ?  VDDOSC and VDD must be powered off at the same time at the point circled in red or green below ?

ramp down.jpg

 

Could you check the following sequence ? Actually, this is the power sequence on the customer’s system.

Sequence.jpg

If there is a problem, what is a problem ?

If the INTOSC frequency drift occurs due to errata, the big drift occurs immediately after INTOSC starts up ?

Or the drift was very small at the INTOSC starts up and it gradually increases by accumulating ?

 

Thanks and regards,

Hideaki

  • +1
    TI__Mastermind 41690 points

    Hello Hideaki-san,

    Please find my comments below:

    Hideaki Matsumoto said:
    Could you check the following sequence ? Actually, this is the power sequence on the customer’s system.

    JC: When VDDOSC voltage is present and VDD is still not powered up, a design bug in the internal oscillator would force current flow to a component that controls the frequency.  This current will eventually shift the component characteristics and cause frequency drift.  This shift accumulates over time whenever VDDOSC voltage is present and VDD is off.

    Hideaki Matsumoto said:
    Does it mean that the ramp up point circled in blue is the same between VDDOSC and VDD ?

    JC: Ideally, below would be the power up condition:

    On the power up case below, the highlighted region would still cause some minimal leakage to the component and if application power cycles the device several times then the accumulated shift on the component may cause some frequency drift.

    Hideaki Matsumoto said:
    How about power off ?  VDDOSC and VDD must be powered off at the same time at the point circled in red or green below ?

    JC: Yes, similar to the condition in power on, power off should be done about the same time.  Typically, there is a large capacitor on VDD so the discharge may take longer, but this is ok since there will not be any current path to the component.  Below diagram on the left shows the ideal power down sequence.  The right diagram shows the typical power down when there is a large capacitor on VDD to allow for discharge.  Both power down sequencing will prevent current from flowing into the component to cause a shift.

    Hideaki Matsumoto said:

    Could you check the following sequence ? Actually, this is the power sequence on the customer’s system.

    Sequence.jpg

    If there is a problem, what is a problem ?

    JC: Yes, there is a problem with this.  The component will be stressed for a duration of ~400us.  If power cycling is done in the application often, then the shift accumulates over time.

    Hideaki Matsumoto said:

    If the INTOSC frequency drift occurs due to errata, the big drift occurs immediately after INTOSC starts up ?

    Or the drift was very small at the INTOSC starts up and it gradually increases by accumulating ?

    JC:  It will not be a big frequency drift at first.  The accumulated time where VDDOSC causes current flow to the component when VDD has not powered up would continuously cause component shift to cause frequency drift.

    Hope this addresses the questions you raised above.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    TI__Genius 9765 points

    Hi Joseph,

    Thank you for sharing the information separately. Unfortunately, the issue the customer is facing has not been resolved yet, but we can close this thread.

    Thanks and regards,

    Hideaki