C2000-GANG: F2838x Ethernet RMII Mode - Speed Verification and Default GPIO Configuration

Hi Aditya,

1. We can read the same register(MAC config REG Bit 14) or the PHY BMCR register

2. We have only tested f2838x board with MII mode only. Mostly the RMII pins are subset except the REF_CLK. Let me check on it and revert back

Reagrds,

Surbhi

Hi Surbhi,

Thanks for the quick response.

1. Beyond checking the register bits, is there a way to observe the actual transmission speed in real time, for example, confirming the data rate on the line or monitoring the negotiated speed as traffic is sent?

2. Could you also check the REF_CLK requirements for RMII on the F2838x?

Regards,
Aditya

Hi Aditya,

1. Verifying Actual Transmission Speed in Real-Time:

Beyond reading the MAC Configuration Register (Bit 14) and PHY BMCR register, you can confirm the actual operating speed through the following methods:
- Oscilloscope on Data Lines: You can probe the TX_DATA/RX_DATA lines to observe the signal frequency. For 100 Mbps RMII, the data toggles at 50 MHz REF_CLK rate; for 10 Mbps, data changes occur every 10 REF_CLK cycles.
- Wireshark / Network Analyzer: On the link partner side, capture traffic using Wireshark or a similar tool. The reported interface speed and measured throughput will confirm the operational datarate.

2. REF_CLK Requirements for RMII:

- RMII requires a 50 MHz reference clock on GPIO_73 (ENET_RMII_CLK).
- This clock must be shared between the MAC and the PHY: both must be driven from the same 50 MHz source

Hi, 
Thank you for the timely response.

I am unable to see the data being toggled, and neither on the oscilloscope can I see 100 Mbps, although the register is getting changes correctly when I switch speed from 10 to 100 Mbps

I wanted to understand all the requirements to run 100 Mbps on the F2838x Rev. B control card, as I am unable to observe 100 Mbps.

Can you please tell what all the requirements are on the hardware and software side to run 100 Mbps 

Regards,

Aditya

Hi Aditya,

On verifying the Schematics for F2838x, we found that GPIO_73 pin is not connected to PHY from the SOC. So in order to RMII to work, you need to do blue wire fix from GPIO_73 to PHY CLK to get the 50MHz clock.

MII mode is supported by default.

We will be doing similar experiment on our end to verify the working of RMII. Will take some time.

Regards,
Surbhi

Hi Surbhi, 
Thank you so much for your quick response.

Can you please tell me about the requirements on the hardware and software side to run 100 Mbps in the MII mode?

Regards,

Aditya

Hi Aditya,

You can run ethernet_ex1_basic_tx_rx_loopback.c example from OOB example support to run in MII mode

To disable loopback in the example: you can comment this line:

//    pInitCfg->loopbackMode = ETHERNET_MAC_CONFIGURATION_LM_LOOPBACK_ENABLED;

The example only send 1 packet out, create a while loop to send more packets.

Apart from layer2 example, there are lwip examples as well enet_lwip_udp,

Regards,

Surbhi

Hi Surbhi, 

Is this example for 10 Mbps or 100 Mbps, as I could not find the bit:.'ETHERNET_MAC_CONFIGURATION_FES'



Regards,

Aditya

Hi Aditya,

I can check on the bit. Can you tell me if the PHY BMSR reg shows 100M ?

Regards,
Surbhi