Part Number: LAUNCHXL-F28P65X
Other Parts Discussed in Thread: DP83826E
Hello,
I am currently migrating a project that was previously running on an LAUNCHXL-F28P65x board to a recently developed custom board based on the TMS320F28P650SH7.
During this process, I have some questions regarding the EtherCAT communication.
The example project and the custom board pin mapping are shown below.
- SDK Example : f28p65x_cpu1_dc_eepromemu_echoback_solution
- PHY : DP83826E
- PIN map :
Based on the EtherCAT pin configuration used in the example project, the following changes were made on the custom board:
-
ESC_TX0_DATA0 ( changed from GPIO87 to GPIO10 )
-
ESC_TX1_DATA0 ( changed from GPIO22 to GPIO75 )
-
ESC_PHY0_LINKSTATUS ( GPIO86 → Not Used )
-
ESC_PHY1_LINKSTATUS ( GPIO68 → Not Used )
According to the TRM document, the ESC_PHYx_LINKSTATUS pins between the MCU and the PHY(DP83826E) are marked as optional. In the example project, these pins are only configured but do not appear to be actively handled in the code. Therefore, we are considering removing these two link status connections in our custom board.
My questions are:
-
Will EtherCAT communication operate correctly if the ESC_PHYx_LINKSTATUS pins are not connected? Or is it mandatory to connect both pins?
-
If the two pins must be connected, could you please share any reference documentation that explains the requirement? (ethercat ip core,....)
Thank you in advance for your support.
