• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 82 subscribers
  • Views 425 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

setup time McBSP timing in master mode

Soenke Barra
Prodigy 40 points


Hello!

One question about the parameter P in the McBSP timing in master mode.

In data manual (Literature Number: SGUS051A - March 2004 - Revised October 2004) on page 148 the McBSP timing is shown. There the parameter

P is defined as ==> 2P = 1/CLKG, in master mode, too.

Therefore, for example the setup time M49 is 123ns (CLKG = 3,75 MHz = extern clock of the McBSP) and the hold time M50 is 123ns, too.

Is that right? I think there is an error in the calculation. The setup time M49 and the hold time M50 are too much.

What P means exactly? 

 

Yours sincerely, S. Barra

 

  • 0
    TI__Expert 5495 points

    Hello Mr. Barra,

    For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2.

    e.g.:
    LSPCLK speed of the 150 MHz device is 75MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4,6875 MHz and P = 13,33 ns.

    I hope  that answers your question.

    Thanks and best regards

    Karim Jamal