TMS320F28374D: Controller is not detecting

Hello,

Vasu Mani said:

We are facing issues like, target is detecting wher we are trying to connect target and debugger is disconnecting when we are trying to do flash erase operation. 

To confirm, the debugger disconnects only when performing a flash erase? Can you scope VDDIO, VDD, XRSn? And also measure IDDIO/IDD during flash operations?

Best,
Matt

Hello,

Yes debugger connects when performing erase operation. We had scoped on VDD and XRSn, VDD was stable at 3.3V and XRSn was going to low when erase operation starts. We dont have option to measure IDDIO and IDD, but will try for the possibilities on monday. If you need snap of those waveforms, i will capture and post here on monday 

Hello,

If XRSn is going low, some reset condition is being asserted by the device (can confirm with the RESC register). Can you share more details on how you're powering the device?

Best,
Matt

Hello,

We have on-board 3.3V and 1.2V regulator which are getting converted from 5V input and connected to controller. I have tried to monitor the RESC register, it was showing 1 after connecting the target which means before preforming flash erase operation. After clicking on flash erase, target was getting disconnected so that i couldn't monitor the RESC register value. I will try to upload the captured images. One more thing i wanted to ask here, i hope external oscillators are not required to place to perform erase and flash operation. Am i right?

Hello,

Please find the attached images. Today we have not seen any disturbance in XRS pin, instead, there is a dip in 3.3V.

Yellow - 1.2V, 

Pink - XRSn,

Green - 3.3V

After connecting with the target 1,2V became noisy and when performing erase operation 3.3V is going low and coming back. 

Hello,

I am out of office until Tuesday (3/10), please expect a delay in assistance until then.

Best,
Matt

Hello,

Vasu Mani said:

One more thing i wanted to ask here, i hope external oscillators are not required to place to perform erase and flash operation.

That is correct. External oscillators are not required for flash operations.

Vasu Mani said:

After clicking on flash erase, target was getting disconnected so that i couldn't monitor the RESC register value.

The RESC register only resets on POR, so an XRSn won't clear the register values.

Vasu Mani said:

After connecting with the target 1,2V became noisy and when performing erase operation 3.3V is going low and coming back. 

Please confirm adequate current is supplied to the device for flash erase/program, as specified by the datasheet:

Best,
Matt

Hello,

Thanks for the reply.

I will check and confirm this tomorrow.

Hi,

Sounds good, I will be here to assist further.

Best,

Matt

Hello,

We are using this TPS62420DRCR regulator to generate 3.3V and 1.2V and it can able to withstand 600mA and 1000mA. Please check the power supply circuit once.

Please refer the below image, Yellow, 3.3V, Green 1.2V, Pink XRSn

Hello,

I've re-assigned this thread to the power/current expert to help review. Please expect a reply shortly.

Best,
Matt

Hello,

Thank you,

We don't have provision to monitor the IDD & IDDIO current, but we have placed a shunt (100mohm) in between power supply and controller.

We observed little voltage increase (in terms of current) when connecting with target, then there was no change while performing flash erase operation.

I guess power supply is not an issue, i may be wrong.

Please give your support and guidance to resolve this.

Hello,

Did you connect VREGENZ to VDDIO? The VREGENZ pin must be tied to VDDIO and an external source used to supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO.

Hello,

Yes we have connected VREGENZ to VDDIO(3.3V), VDD is connected to regulator output which is giving 1.2V. 

We have 3.3V output from regulator which is directly connected to VREGENZ and VDDIO pins are also connected to 3.3V output from the regulator but through bead inductor.

I don't understand the ramp concept. Can you please explain little more clearly?

Vanu,

The ramp is related to the Power sequencing described in data sheet: 6.9.1 Power Sequencing, www.ti.com/.../tms320f28379d.pdf

Your supply ramp rate should be within range from 330 to 10^5 V/s, as well. 

Hello,

As per signal per requirement, all the digital and analog pins are open now. we will find out the supply ramp rate and update you here.

Okay, sounds good. Looking forward to your update.

Hello,

Please look at the attached images, which are 3.3V and 1.2V

3.3V is taking 1ms to reach from 0V after powerup. 1.2V is taking around 1.6ms to reach from 0V after powerup.

We have captured those things with external power supply, we will try capture with on-board regulator.

Hello,

Thanks for the reply,

Please Give us some time to debug the power supply, We have continuous holidays in india, i will try to make it work on friday, if not i will post update on monday

Hello Vasu,

Thank you for the update. Looking forward to your reply.

Hello Stevan,

Please find the attached image, we made the power supply to reach 3.3V & 1.2V within the time limit, But still the erase and flash operation is failing.

Hello Vasu,

What are the new supply ramp rates? Couple of notes:

- Before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).

- The 3.3-V supplies should be powered up together and kept within 0.3 V of each other during functional operation.

- During the ramp, VDD should be kept no more than 0.3 V above VDDIO.

Hello Stevan,

The ramp rate 2750 V/S. which means it reaching 3.3V in 1.2ms. 

We have not connected any circuits to digital IO and analog pins, all are open.

VERFHI is connected to 3.3V which is connecting to VDDIO through bead inductor.

Yes we powered up 3.3V and 1.V together.

Yes VDD supply is below VDDIO supply and you can refer above image yellow (3.3V) is higher than green (1.2V).

We have tried the same in another controller and we have spares as well. We noticed that XRSn pin is resetting continuously at the rate of 50Hz after performing erase operation. It was at high(3.3V) before performing erase operation. 

Please refer the attached image.

Hello Vasu,

What is the selected boot mode you are using? Could you try to configure boot mode pins for Wait Boot ("01") mode when programming via JTAG? 

Hello Stevan,

As of now we have connected both the GPIO's to 3.3V through pull-up and which is in Flash Boot.

Yeah let us try with wait boot mode option

Hello Stevan, 

We have tried by changing the boot mode pins, but still, we are getting the same error while performing the flash / erase operation.

I wanted to clarify one more thing here,

This is the JTAG connector from our schematic, those pins are connecting with TMS320F28374D and connected with external digital spectrum XDS200 debug probe.

We have used external circuits as mentioned in the datasheet, please refer the below image,

Please correct me if anything to be changed / updated. Since power supply requirements are met, as you informed there is no voltage in digital IO and analog pins, which means are the pins open and unused. 

Hello,

I will take a look and reply in timely manner.

Hello Stevan,

Thank you, looking forward to your reply.

Hello Vasu,

Could you share the schematic for C2000 part, please? I want to give a quick check if something is missing on C2000 side?

Hello Stevan,

Please find the attached schematic.

Our team connected the boot pin wrong, so removed those pull-up resistors and connected correct pins(GPIO72, GPIO84) externally.

i guess other things are fine.

Control_Card_design_final 2.pdf

Hello Vasu,

Thank you for sharing your schematic file. By reviewing, I found the issue with the VDD and VDDA power rails. The decoupling capacitor are missing for VDD_MCU and VDDA_MCU which causes noise prone power rails. This is most probably the root cause of the issue you are seeing. 

According to data sheet, page 35:  https://www.ti.com/lit/ds/symlink/tms320f28374d.pdf 

VDD: 

There are two options for placing the decoupling capacitors.

    • Option 1 - Even Distribution: Distribute decoupling capacitance evenly across each VDD pin with a minimum total capacitance of approximately 20uF.

    • Option 2 - Bulk Capacitance: Place a 1uF capacitor near each VDD pin and place the remainder of the minimum total 20uF capacitance as bulk capacitance on the           VDD net

VDDA:

Place a minimum 2.2-µF R6 54 38 decoupling capacitor to VSSA on each pin.

There is a 22uF decoupling capacitor placed on VDD_1V2, but I could not find any connection between VDD_1V2 and VDD_MCU_1V2 in schematic. Was this done intentionally? Also, could you elaborate boot mode GPIOs being added externally, please?

Looking forward to your reply.

Hello Stevan,

Thanks for the inputs,

We will place the capacitors as mentioned and try.

Was this done intentionally? Also, could you elaborate boot mode GPIOs being added externally, please?

Yes, we have added pull-up resistors with 4.7k externally to correct GPIO pins (GPIO72, GPIO84). As per schematic there is boot mode configuration on those pins.

Hello Stevan,

VDD_1V2 and VDD_MCU_1V2 are connected through an inductor L4

Hello Vasu,

Thanks for your reply. That should be good then. Please allow me some more time to check schematic further to see if there any issue. It is recommended to use 56k for pull-ups for boot mode in general.