.syscfg file to launch the graphical user interface.ti_drivers_config.c. The tool also performs validity checks to prevent incorrect configurations.
I am sorry I am not able to upload the screenshot of my sysconfig example.
The MCAN clock is configured in MCANA Clock under Clock Tree:
1. Select the clock source: AUXCLKIN, SYSCLK, and PLLCLK
2. Select the CLK divider: MCANxCLKDIV
For Init Parameters settings:
• Enable CAN FD Mode: where CAN flexible data mode needs to be enabled.
• Enable Bit Rate Switching: by enabling this feature, MCAN sends data at higher rate instead of the arbitration rate. This function only works when CAN FD mode is enabled.
• Enable Loopback Mode: transmitted messages become received messages. This allows users to monitor the CAN messages on the CAN_TX pin without a CAN transceiver.
• Enable Transmit Pause: pauses for two CAN bit times before the next transmission. The transmit pause feature is intended for use in CAN networks where the CAN Message IDs are specific and cannot easily be changed.
• Enable Edge Filtering: two consecutive dominant time quanta required to detect an edge for hard synchronization. Enabling this function is to make sure that nodes can accurately detect signal edges and perform hard synchronization under the condition of longer data bit times, thereby improving the stability and reliability of CAN bus communication.
• Enable Protocol Exception Handling: detection of bits that are reserved for future protocol expansion.
• Messages Will Only Be Sent Once: if automatic retransmission is disabled, then the MCAN module no longer retransmits when there is a transmission error, NACK, or the MCAN module loses arbitration.
• Enable Wakeup Request: enables the MCAN module to wakeup on CAN RXD activity.
• Enable Auto-Wakeup: enables the MCAN module to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up on an enabled wakeup request.
• Enable Transmitter Delay Compensation: Enable the compensation for the delay between CAN TX and CAN RX.
• Message RAM Watchdog Preload Value: the RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured.
For Transmitter Delay Compensation (TDC):
TDC is a mechanism used to compensate for the delay caused by the loop delay of the transceiver in CAN FD systems. This delay can prevent nodes from performing meaningful bit error checks at the sample point during high-bit-rate data transmission. Specifically, TDC introduces a secondary sample point (Secondary Sample Point or SSP) in the data phase, where the transmitted bit is compared with the received bit after accounting for the delay. This makes sure that the bit errors are correctly detected and handled.
TDC is necessary when the bit rate is high, leading to short data bits and significant loop delays. These delays can cause the node to miss the correct sample point for bit error detection. TDC is only active during the data phase and does not affect the arbitration phase.
By using TDC, the data phase can have a shorter bit time than the nominal bit time, enabling higher data rates without compromising error detection.
• TDC Filter Window Length (Cycles): this filter feature defines a minimum value for the SSP position to avoid the case in which a dominant glitch inside the received FDF bit ends the delay compensation measurement before the falling edge of the received res bit, resulting in an early taken SSP position.
• TDC Offset (Cycles): this offset is used to adjust the position of the SSP inside the received bit (for example, half of the bit time in the data phase).
For Bit Timing Parameters:
Bit timing in the CAN bus refers to the critical parameters used for synchronization and control of data transmission in CAN communication. This divides the time of each bit into multiple time periods (called Time Quanta or TQ) to make sure that all nodes on the network can accurately receive and transmit data. The setting of bit timing includes several key components:
The sync segment is 1TQ always. The role of bit timing in data transmission is reflected in aspects such as synchronization and consistency, data integrity, fault tolerance, data rate and network performance, and anti-interference capability.
The Sample Point (SP) is (1 +SEG1)/(1+SEG1+SEG2)
For Message RAM Configuration
The MCAN module has a Message RAM. The main purpose of the Message RAM is to store:
1. Message ID filter elements
2. Transmit messages
3. Tx event elements
4. Received messages
The Message RAM size is configured for 4kB size with a width of 32 bits is described in this application note.
1. Message ID filter elements
Standard and Extended ID Filter Configuration
• Std ID Filter List Start Address: each standard ID filter takes 4 message RAM address.
• Number of Standard ID Filters: up to 128 filter elements can be configured for 11-bit standard IDs.
• Standard ID Filter configuration (after the section of RX MSG RAM) → Filter Element Configuration: all enabled filter elements are used for acceptance filtering of standard frames. Acceptance filtering stops at the first matching enabled filter element or when the end of the filter list is reached. Options for this parameter are shown below.
– 0x0: disable filter element
– 0x1: store in Rx FIFO 0 if filter matches
– 0x2: store in Rx FIFO 1 if filter matches
– 0x3: reject ID if filter matches
– 0x4: set priority if filter matches
– 0x5: set priority and store in FIFO 0 if filter matches
– 0x6: set priority and store in FIFO 1 if filter matches
– 0x7: store into Rx Buffer, configuration of standard filter type ignored
• Standard ID Filter configuration → Filter Type: standard filter type configuration. Options for this parameter are shown below.
– 0x0: range filter from SFID1 to SFID2 (SFID2 ≥ SFID1)
– 0x1: dual ID filter for SFID1 or SFID2
– 0x2: classic filter: SFID1 = filter; SFID2 = mask
– 0x3: filter element disabled
• Standard ID Filter configuration → Filter ID 1 (SFID1): Standard Filter ID 1. When filtering for Rx buffers, this field defines the ID of a standard message to be stored. The received identifiers must match exactly, and no masking mechanism is used.
• Standard ID Filter configuration → Filter ID 2 (SFID2): Standard Filter ID 2. This ID has different definitions depending on the filter element configuration. If the filter element configuration is from 0x1 to 0x6, then SFID2 is the second ID of standard ID filter element. If the filter element configuration is 0x7, then SFID2 is a filter for Rx buffers
The configuration for the Extended ID filter is shown below:
• Extended ID Filter List Start Address: each extended ID filter takes 8 message RAM addresses.
• Number of Extended ID Filters: up to 64 filter elements can be configured for 29-bit extended IDs.
• Extended ID Filter configuration (after the section of RX MSG RAM) → Filter Element Configuration: all enabled filter elements are used for acceptance filtering of extended frames. Acceptance filtering stops at the first matching enabled filter element or when the end of the filter list is reached.
– 0x0: disable filter element – 0x1: store in Rx FIFO 0 if filter matches
– 0x2: store in Rx FIFO 1 if filter matches
– 0x3: reject ID if filter matches
– 0x4: set priority if filter matches
– 0x5: set priority and store in FIFO 0 if filter matches
– 0x6: set priority and store in FIFO 1 if filter matches
– 0x7: store into Rx Buffer or as debug message, configuration of extended filter type ignored
• Extended ID Filter configuration → Filter Type: extended filter type configuration. Options for this parameter are shown below.
– 0x0: range filter from EFID1 to EFID2 (EFID2 ≥ EFID1)
– 0x1: dual ID filter for EFID1 or EFID2
– 0x2: classic filter: EFID1 = filter, EFID2 = mask
– 0x3: range filter from EFID1 to EFID2 (EFID2 ≥ EFID1), Extended ID and Mask not applied
• Extended ID Filter configuration → Filter ID 1 (EFID1): extended Filter ID 1. First ID of the extended ID filter element. When filtering for Rx buffers, this field defines the ID of an extended message to be stored.
• Extended ID Filter configuration → Filter ID 2 (EFID2): Extended Filter ID 2. This ID has different definitions depending on the extended filter element configuration. If the extended filter element configuration is from 0x1 to 0x6, then EFID2 is the second ID of extended ID filter element. If the extended filter element configuration is 0x7, then EFID2 is a filter for Rx buffers.
For TX MSG RAM:
The Tx buffers section can be configured to hold dedicated Tx buffers as well as a Tx FIFO and Tx Queue. When the Tx buffers section is shared by dedicated Tx buffers and a Tx FIFO and Tx Queue, the dedicated Tx buffers start at the beginning of the Tx buffers section followed by the buffers assigned to the Tx FIFO or Tx Queue.
Differences between Tx buffer mode, Tx FIFO mode and Tx queue mode:
Tx buffer mode: Dedicated Tx buffers are intended for message transmission under complete control of the host CPU.
Tx FIFO mode: Tx FIFO allows transmission of messages with the same Message ID from different Tx buffers in the order these messages have been written to the Tx FIFO.
Tx queue mode: The stored in the Tx Queue messages are transmitted starting with the highest priority message (lowest Message ID).
• TX Buffers Start Address: the start address of Tx buffers in message RAM.
• Number of Dedicated Transmit Buffers: defines how many elements are configured as dedicated Tx buffers.
• No of TX FIFO Elements: defines how many elements are configured as Tx FIFO or Tx queue.
• TX FIFO Operation Mode: defines the Tx FIFO mode or Tx queue mode.
• TX Buffer Element Size: defines the Tx buffer data field size. In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size, the bytes not defined by the Tx Buffer are transmitted as 0xCC (padding bytes).
• TX Event FIFO Start Address: the Tx Event FIFO stores information about transmitted messages. To support Tx event handling, the Message RAM has implemented a Tx Event FIFO section. By reading the Tx Event FIFO, the Host CPU gets this information in the order the messages were transmitted. After message transmission on the CAN bus, Message ID and Timestamp are stored in a Tx Event FIFO element. To link a Tx Event to a Tx Event FIFO element, the Message Marker from the transmitted Tx Buffer is copied into the Tx Event FIFO element.
• TX Event FIFO Size: up to 32 Tx Event FIFO elements can be configured.
• Level for TX Event FIFO Watermark INT Level: defines Tx Event FIFO fill level threshold. The Tx Event FIFO watermark can be configured to avoid a Tx Event FIFO overflow.
For RX MSG RAM:
Up to 64 Rx buffers and two Rx FIFOs can be configured in the Message RAM. Each Rx FIFO section can be configured to store up to 64 received messages. The element size can be configured for storage of CAN FD messages with up to 64 bytes data field.
• RX FIFO0 and RX FIFO1 Start Address: defines the start address of Rx FIFOs in message RAM.
• Number of RX FIFO0 and RX FIFO1 Elements: each Rx FIFO can be configured to store up to 64 received messages.
• RX FIFO0 and RX FIFO1 Watermark: the Rx FIFO watermark can be used to prevent an Rx FIFO overflow. If the Rx FIFO fill level reaches the Rx FIFO watermark, then an interrupt flag MCAN_IR.RF0W/ MCAN_IR.RF1W is set.
• RX FIFO0 and RX FIFO1 Operation Mode:
– Rx FIFO Blocking Mode: the Rx FIFO blocking mode is the default operation mode for the Rx FIFOs. If an Rx FIFO full condition is reached, then no further messages are written to the corresponding Rx FIFO until at least one message is read out and the Rx FIFO Get Index is incremented.
– Rx FIFO Overwrite Mode: when an Rx FIFO full condition is reached, the next accepted message for the FIFO overwrites the oldest FIFO message.
• RX FIFO0 and RX FIFO1 Element Size: defines the Rx FIFO element size.
• RX Buffer Start Address: defines the start address of Rx buffer in message RAM.
• RX Buffer Element Size: defines the Rx buffer element size.
For Additional Core Configuration:
• Enable Additional Core Configuration: enable or disable additional functions like timestamp and process nonmatching frames.
• Enable Bus Monitoring Mode: in bus monitoring mode, the MCAN module is able to receive valid data and remote frames, but cannot start a transmission. The MCAN module sends only recessive bits on the CAN bus. If the MCAN module is required to send a dominant bit (ACK bit, overload flag, active error flag), then the bit is rerouted internally so that the MCAN module monitors this dominant bit. The CAN bus can remain in recessive state. The bus monitoring mode can be used to analyze the traffic on a CAN bus without affecting the bus by the transmission of dominant bits.
• Enable Restricted CAN Operation: defines normal CAN operation mode to restricted operation mode. In restricted operation mode, the CAN node is able to receive data and remote frames and to give acknowledgment to valid frames, but the node does not send data frames, remote frames, active error frames, or overload frames. In case of an error condition or overload condition, the node does not send dominant bits; instead, the node waits for the occurrence of bus idle condition to resynchronize to the CAN communication. The restricted operation mode is automatically entered when the Tx Handler is not able to read data from the Message RAM in time. To leave restricted operation mode, the host CPU has to reset the MCAN_CCCR.ASM bit. This mode can be used in applications that adapt themselves to different CAN bit rates. In this case, the application tests different bit rates and leaves the restricted operation mode after the node has received a valid frame.
• Time Stamp Prescaler Value: the MCAN module has integrated a 16-bit wrap-around counter for timestamp generation. The timestamp counter prescaler MCAN_TSCC.TCP field can be configured to clock the counter in multiples of CAN bit times (1-16). On start of a frame reception or transmission, the counter value is captured and stored into the timestamp section of an Rx Buffer, Rx FIFO or Tx Event FIFO element.
• Timestamp Counter Value: configures the timestamp counter value to 0x0, from the internal 16-bit counter or from an external timestamp.
• Time-out Counter Source Select: the MCAN module has an integrated a 16-bit timeout counter. The timeout counter is used to signal timeout conditions for the Rx FIFO 0, Rx FIFO 1, and Tx Event FIFO Message RAM elements. In continuous mode, the counter is immediately restarted at the value configured by the MCAN_TOCC.TOP field. In case the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by the MCAN_TOCC.TOP field. Down-counting is started when the first FIFO element is stored.
• Start Value of the Timeout Counter: defines the timeout duration. • Enable Time-out Counter: enables the timeout function.
• Reject Remote Frames Extended: filter or reject all remote frames with 29-bit extended IDs.
• Reject Remote Frames Standard: filter or reject all remote frames with 11-bit standard IDs.
• Accept Non-matching Frames Extended: defines how received messages with 29-bit IDs that do not match any element of the filter list are treated.
• Accept Non-matching Frames Standard: defines how received messages with 11-bit IDs that do not match any element of the filter list are treated.
