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TMS320F28P550SG: Using the software phase locked loop in the DCL library with variable frequency AC

Iain Mosely
Prodigy 140 points

Part Number: TMS320F28P550SG

Dear TI Team,

I am building a totem pole PFC system using the TMS320F28P550SG which needs to operate with variable AC frequency. I plan to use the software phase locked loop library functions to help with the control of this system based around one of the TI example designs. 

For the TI examples I have seen, all are designed to run with a normal AC frequency of 50 or 60Hz for which the SPLL should work well. However, I need good PLL performance with an AC frequency which varies over a range of approximately 2:1 and am concerned that this maybe compromise PLL performance at the extremes of AC frequency.

Can you provide any guidance on the trade offs I may need to consider with variable frequency operation and what I need to be careful about. The AC frequency will only change frequency quite slowely, of the order of seconds.

Many Thanks,

Iain

  • +1
    TI__Genius 12015 points

    Pls check the other PLL (SOGI based) in our library. Please also search IEEE literature on SPLL. A few things to check: 

    • A higher bandwidth allows the SPLL to track frequency changes faster but makes it more susceptible to grid noise and harmonics.
    • A lower BW provides better filtering of high-frequency jitter but can result in a significant phase lag during frequency ramps.
    • Since your frequency change is slow (seconds), you can prioritize a lower BW to ensure high-quality sinusoidal output with minimal harmonic distortion.
    • In a wide range (50–120Hz), the loop gain of a standard PI-based SPLL may vary, potentially leading to instability at the higher end of the spectrum.
    • Consider implementing a frequency adaptive SPLL. This approach automatically adjusts internal coefficients (like the sampling rate or filter gains) based on the estimated frequency to maintain a constant damping ratio and stable phase margin across the entire 50–120Hz range.
    • During a frequency transition, a standard Type-I or Type-II PLL will exhibit a steady-state phase error proportional to the rate of frequency change.
    • If absolute phase synchronization is critical during the ramp, a higher-order loop or a lead-lag compensator may be necessary to minimize this lag.
    • Ensure your sampling frequency is high enough to avoid aliasing at 120Hz. A common rule of thumb for high-performance inverters is a sampling rate at least 10–20 times the maximum fundamental frequency (i.e., >2.4 kHz).
    • The SPLL must be able to "capture" the frequency starting from a wide initial offset. Using a Frequency-Locked Loop (FLL) in tandem with the PLL can help the system reliably acquire lock at either 50Hz or 120Hz without manual intervention.
  • 0 in reply to Shamim Choudhury
    Prodigy 140 points

    Thanks Shamim, this is really useful information. I'm going to build a project to explore PLL behaviour using our hardware and based on your input above, I think we should be able to manage the wider than normal frequency range.

    Many Thanks, Iain