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TMS320F28P650DK: Clock Dividers and PWMs

Reid Anderson
Prodigy 80 points

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: SYSCONFIG

Hello,

I'm looking to try and understand how the clocks get set and what is bringing about the 1/2 speed i'm seeing from my PWMs. I'm using the TMS320F28P650DK6PZ chip, using the internal oscillator. I'm starting a blank project (empty_driverlib_project from Project Explorer) and I am looking to get some ePWMs out. In my device.h file, I uncommented the #define USE_PLL_SRC_INTOSC which switches in a value of 10000000U (10 MHz) for DEVICE_OSC_SRC_FREQ. The following line sets:

#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 40) / (1 * 2 * 1))

Which should total 200 MHz.

In my SysConfig, I configured a 50% duty PWM by setting TBP to 100 on up-down count mode with an action qualifier to set it high when TB counter up equals a COMPA of 50 and low when the TB counter down equals COMPA. 

My high speed clock divider and TB clock dividers are both set at 1, so I know I'm not getting a division there that would cause this.

On the scope, i see a period of 2us, or a 500kHz signal, 50% duty. This seems off to me, as I would expect a 100 TBP to give me a period of 1 MHz. 

From the C2000 Academy videos for the up-down counter,

TBPRD = Tpwm / (2 * Ttbclk)

If TBPRD = 100 and Tpwm = 2e-6, solving for Ttbclk would yield 1e-8, or 10ns. This corresponds to 100MHz clock. 

I'm trying to avoid the ClockTree tool and I want to see if there's default code i can change here.

Thanks

  • 0
    TI__Expert 6370 points

    Hello Reid,

    I took a look at the driverlib project and the issue you are seeing is because EPWMCLK is set to the 100 MHz by default. Figure 6-22 on page 131 of data sheet: https://www.ti.com/lit/ds/symlink/tms320f28p650dk.pdf , shows how clocking system is configured.

    PLLSYSCLK is set set to 200 MHz, and to maintain EPWMCLK frequency of 200 MHz, EPWMCLKDIV should be set to 1, and not 2 as it is by default: Page 425, TRM, https://www.ti.com/lit/ug/spruiz1b/spruiz1b.pdf. 

    You could quickly change it in ClockTree Tool:

    1. Select INTOSC as the source and adjust the CLK coefficients: REFDIV = 1, IMULT = 40; ODIV = 2; SYSCLKDIVSEL = 1;

    2. Change EPWMCLKDIV to 1 and it should indicate 200MHz EPWM frequency.

  • 0
    TI__Expert 6370 points

    Reid,

    Is there any reason that you need to configure ePWM clock to be 200MHz by default? You could just use 100 MHz EPWMCLK in your calculations to get correct period.

  • 0
    TI__Expert 6370 points

    Lastly, if you want to change the ePWM clock divider by not using ClockTree, you could pass the divider you need to the function in sysctrl.h and call it from main.

    //! This function configures the clock rate of the EPWMCLK. The
    //! \e divider parameter is the value by which the SYSCLK rate is divided to
    //! get the EPWMCLK rate. For example, \b SYSCTL_EPWMCLK_DIV_2 will select an
    //! EPWMCLK rate that is half the PLLSYSCLK rate.

    SysCtl_setEPWMClockDivider(SysCtl_EPWMCLKDivider divider)
    {
    //
    // Write the divider selection to the appropriate register.
    //
    EALLOW;
    HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) =
    (HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &
    ~SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M) | (uint16_t)divider;
    SYSCTL_REGWRITE_DELAY;
    EDIS;
    }

  • 0 in reply to Stevan Duraskovic
    TI__Genius 12790 points

    I am replying on behalf of Reid who is unable to reply to the E2E thread at the moment. 

    Essentially, I have my clocks set as the default settings in the empty_driverlib_project. I am trying to get my ePWM clocks to operate with a clock divider of 200 MHz. I can’t seem to do that.

    I am selecting the internal oscillator, which seems to have a 10MHz. In device.h, we seem to select a clock multiplication of 200 MHz because we multiply by 20. My clock dividers for my ePWM seem to be set as 1 and 1, respectively, as shown below in device.h.

    My PWM frequency with an up-down count is 2us, and with the divider of 2 already accounted for, that would make the Ttbclk = 100MHz.

    TBPRD = Tpwm / (2 * Ttbclk) – for up-down.

    Substituting a TBPRD of 100 in and a Tpwm of 2us (rising edge to rising edge), we would get a Ttbclk of 1e-8, or 10 nanoseconds, corresponding to a clock of 100 MHz.

    I also tried with an up-count mode, using 100 as my TBP, and I saw a period of around 1us, which again corresponds to 100 MHz.

    I have even tried insertion of the following line:

    // Set EPWM Clock Divider to 1 which will be 200MHz switching frequency
       SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_1);

    This line simply causes some kind of crash and the project does not function.

     

     

  • 0 in reply to rperezti
    TI__Expert 6370 points

    Hello,

    The results you get are because EPWMCLK is 100MHz by default. Is there any reason why 200 MHz EPWMCLK needs to be achieved? Did you try making changes in ClockTree or calling SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_1) in main.c as I previously suggested?

  • 0 in reply to Stevan Duraskovic
    TI__Genius 12790 points

    Yes Reid tried calling SysCtl_setEPWMClockDivider in main and it caused the application to crash with CCas disconnecting. 

  • 0 in reply to rperezti
    TI__Expert 6370 points

    Hello,

    I will check on my end too and get back to you. Meanwhile, please try ClockTree tool as well as advised.

  • 0 in reply to Stevan Duraskovic
    Prodigy 80 points

    Stevan and Ruben,

    I see the following message when i attempt to run the SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_1) line in main() post device initialization:

    No source available for "_system_post_cinit() at C:\Users\(Project Location Here):{3} 0x3feaa2{4}" 

  • 0 in reply to Stevan Duraskovic
    Prodigy 80 points

    Stevan,

    If at all possible, I'd like to try and see if there's code I could write instead of using the ClockTree tool. If we can't find any options and it seems that the ClockTree is the only way to really edit it or set this up, then I will do so, but it seems like a matter of clock settings and initializations which seem easy enough to set in a couple lines.

    Thanks,

    Reid

  • 0 in reply to Reid Anderson
    Prodigy 80 points

    I have tried to configure the Clock Tree tool, but I'm left with a number of errors when I build. I see a lot of variables that get redefined in places, causing errors. It also tells me that it either can't fit into available memory or the section contains a call site that requires a trampoline that can't be generated for a section regarding my generic_ram_lnk_.cmd file. For this particular trial project, I am leaning heavily on SysConfig to do all initialization and configuration for me.

  • 0 in reply to Reid Anderson
    TI__Expert 6370 points

    Reid,

    Could you take a snapshot of the error you receive? Do you get this error when building without using this function? I called the function in my case, and it did not cause issues. 

    For ClockTree you could follow my instructions above. When you change the clock source it will give you errors, but if you change coefficients as shown in steps 1 and 2, it should be fine.

  • 0 in reply to Reid Anderson
    Prodigy 80 points

    This is the error i get when i attempt to use the Clock Tree tool and customize it to select an ePWM clock of 200 MHz. I know that what's going on here is an over-declaration, but I'm only using SysConfig to set these configurations up, so I'm not sure what the prescription is or how to properly use the GUI tools to avoid this over-declaration.

  • 0 in reply to Reid Anderson
    TI__Expert 6370 points

    Reid,

    Thank you for your reply. It seems the issue is with, as you stated, over-declaration. Do you configure your device support in Syscfg GUI or you have separate device support folder added to the project?

    Having both activated would produce this error. If you want to use ClockTree tool, then you should configure Device Support solely in your Syscfg GUI. What about your memory cmd files? Are they defined in syscfg or you have separate files? Looking forward hearing from you.

  • 0 in reply to Stevan Duraskovic
    Prodigy 80 points

    Stevan,

    That's possible, would excluding the following folder assist in reducing this over-declaration?

    As far as memory CMD files, I have the generic 28p65x_generic_ram_lnk_cpu1.cmd file present in my project. Essentially, everything that is present when you first open a blank project for this chip.

    Thanks,

    Reid

  • 0 in reply to Reid Anderson
    TI__Expert 6370 points

    Hello Reid,

    That seems is an issue. Please remove device folder from the project and keep device support in Syscfg. Please let me know if it works out for you.