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TMS320F28P650DK: Driverlib memory initialization values not seem to match

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: C2000WARE

Hi champs,

 

I am asking this for our customer.

In C:\ti\c2000\C2000Ware_6_00_01_00\driverlib\f28p65x\driverlib

memcfg.h

memcfg.c

MEMCFG_SECT_LSX_ALL, MEMCFG_SECT_GSX_ALL, MEMCFG_SECT_MSGX_ALL do not seem to match the reigsters.

Take MEMCFG_SECT_LSX_ALL as an example, the definitions 0x010003FFU are shown below.

From Table 3-520. LSxINITDONE Register Field Descriptions of the TRM

www.ti.com/.../spruiz1

the bit 10-31 are reserved, so qeustions:

  1. why is there the 1 in 0x010003FFU?
  2. Is this used on purpose?
  3. Is it reserved by TI use or is it a typo in the code?
//
// LSxRAM - Local shared RAM config
//
#define MEMCFG_SECT_LS0             0x01000001U //!< LS0 RAM
#define MEMCFG_SECT_LS1             0x01000002U //!< LS1 RAM
#define MEMCFG_SECT_LS2             0x01000004U //!< LS2 RAM
#define MEMCFG_SECT_LS3             0x01000008U //!< LS3 RAM
#define MEMCFG_SECT_LS4             0x01000010U //!< LS4 RAM
#define MEMCFG_SECT_LS5             0x01000020U //!< LS5 RAM
#define MEMCFG_SECT_LS6             0x01000040U //!< LS6 RAM
#define MEMCFG_SECT_LS7             0x01000080U //!< LS7 RAM
#define MEMCFG_SECT_LS8             0x01000100U //!< LS8 RAM
#define MEMCFG_SECT_LS9             0x01000200U //!< LS9 RAM
#define MEMCFG_SECT_LSX_ALL         0x010003FFU //!< All LS RAM
/*****************************************************************************
//
// MemCfg_initSections
//
//*****************************************************************************
void
MemCfg_initSections(uint32_t ramSections)
{
    //
    // Check the arguments.
    //
    ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D)   ||
           ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS)  ||
           ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)  ||
           ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) ||
           (ramSections == MEMCFG_SECT_ALL));

    //
    // Set the bit in the various initialization registers that starts
    // initialization.
    //
    EALLOW;

    switch(ramSections & MEMCFG_SECT_TYPE_MASK)
    {
        case MEMCFG_SECT_TYPE_D:
            HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT)   |= MEMCFG_SECT_NUM_MASK &
                                                      ramSections;
            break;

        case MEMCFG_SECT_TYPE_LS:
            HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT)  |= MEMCFG_SECT_NUM_MASK &
                                                      ramSections;
            break;

        case MEMCFG_SECT_TYPE_GS:
            HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT)  |= MEMCFG_SECT_NUM_MASK &
                                                      ramSections;
            break;

        case MEMCFG_SECT_TYPE_MSG:
            HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK &
                                                      ramSections;
            break;

        case MEMCFG_SECT_TYPE_MASK:
            //
            // Initialize all sections.
            //
            HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT)   |= MEMCFG_SECT_NUM_MASK &
                                                      MEMCFG_SECT_DX_ALL;
            HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT)  |= MEMCFG_SECT_NUM_MASK &
                                                      MEMCFG_SECT_LSX_ALL;
            HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT)  |= MEMCFG_SECT_NUM_MASK &
                                                      MEMCFG_SECT_GSX_ALL;
            HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK &
                                                      MEMCFG_SECT_MSGX_ALL;
            break;

        default:
            //
            // Do nothing. Invalid ramSections. Make sure you aren't OR-ing
            // values for two different types of RAM.
            //
            break;
    }

    EDIS;
}
  • Hi Wayne,

    Thank you for your question. Let me check with the SDK team and get back to you.

    Thanks,

    Ira

  • Hi Wayne,

    That bit is just to identify whether it is a D/LS/GS/MSG type of memory (check first 8 bits - in bold). The mask MEMCFG_SECT_TYPE_MASK which is 0xFF000000u is added for this purpose.

    #define MEMCFG_SECT_TYPE_MASK   0xFF000000U
    #define MEMCFG_SECT_TYPE_D      0x00000000U
    #define MEMCFG_SECT_TYPE_LS     0x01000000U
    #define MEMCFG_SECT_TYPE_GS     0x02000000U
    #define MEMCFG_SECT_TYPE_MSG    0x03000000U
    Based on the type of memory it is, we will choose the correct INIT hardware register in switch case block.
    After this when we want to actually write to the MEMCFG_O_DXINIT / MEMCFG_O_LSXINIT / MEMCFG_O_GSXINIT / MEMCFG_O_MSGXINIT registers, we anyway add the MEMCFG_SECT_NUM_MASK which is 0x00FFFFFFu, so those bits are not written.
    Thanks,
    Ira