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TMS320F28P550SJ: The SPI communication when SPIPTE is pulled low

Luke Chen
Prodigy 40 points

Part Number: TMS320F28P550SJ

Hi champ,

Our engineers connect the SPIPTE pin to low and let SPI module operates in FIFO mode. Communication between master and slave devices is fine in mode 0, 2 and 3. However, in mode 1 (polarity=0, phase=1), the SPI slave device loses synchronization and received incorrect data bits.

In the TRM, we see that TI does not recommend always pulling the SPIPTE pin low. If so, are there potential problems when using CLB and SPI in encoder applications, such as pulling SPIPTE low for a T-format encoder?

Please advise your comments, what is the reason the SPI slave device loses synchronization in mode 1 when SPIPTE is pulled low, while working normally in other modes?

Thanks and regards,

Luke

  • 0
    TI__Mastermind 20365 points

    Hi Luke,

    By keeping the SPIPTE indefinitely low, this system is violating the timing requirements listed in the datasheet. The SPIPTE provides the ability to gate spurious clock and data pulses and prevents the SPI from losing synchronization with the controller. I am not sure why this is issue is not more obvious in the other modes but refer to the datasheet for the proper delay time.

    For recovery, the SPISWRESET bit can be toggled.

    Best Regards,

    Aishwarya