Part Number: TMS320F280049C
Hey,
I have written my code using the bitfield approach. However, for one complex PWM generation, we need to use the Configurable Logic Block (CLB) to generate EPWM8 from EPWM1 & EPWM4. Unfortunately, I could not find any example codes or clear information online for implementing this using the bitfield approach.
Please let me know how to generate these PWM pulses using CLB.
Regards,
Akash
Hi Akash,
Assuming that you are inputting EPWM1 as input 0 and EPWM4 as input 1, then you should be able to logically AND the two signals by doing the following using bitfields:
This should allow you to input the two EPWMs into a CLB LUT
Hi AJ
I have tested the code you provided. Did not get the output. Attaching my code for your reference.
//#############################################################################
/
//
#include "F28x_Project.h"
#include "IQmathLib.h"
#include "math.h"
//#include "Solar_F.h"
#include "SFO_V8.h"
//
//
#define PI 3.1459
float32 TIMER_PERIOD_COUNT=500;
float32 TIMER_PERIOD_COUNT_ISR=500;
volatile float Fc=1000, Sw_period=0.00001, Sw_period_isr = 0.00001;
int deadband=40;
int deadband_1A=40;
int deadband_2A=40;
int tbphs=2;
#define PWM_CH 3// # of PWM channels + 1
volatile struct EPWM_REGS *ePWM[PWM_CH] = { &EPwm1Regs, &EPwm1Regs, &EPwm2Regs};
int MEP_ScaleFactor;
Uint16 status;
volatile float v_a, v_pu;
volatile float radian;
volatile int k=0;
Uint32 delay2=0;
int temp = 0;
// Function Prototypes
void Setup_ePWM(void);
void Gpio_select(void);
void ConfigureADC(void);
void SetupADCSoftware(void);
__interrupt void adcA1ISR(void);
__interrupt void epwm1_isr(void);
void error(void);
//
// Main
//
void main(void)
{
//
//Step 1. Initialize System Control:
//PLL, WatchDog,enabe Peripheral Clocks
//This example function is found in the f28004x_sysctrl.c file.
//
#ifdef _FLASH
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t) &RamfuncsLoadSize);
#endif
//
InitSysCtrl();
//
//Step 2. Initialize GPIO
//
InitGpio();
//
//Step 3. Clear all __interrupts and initialize PIE vector table:
//Disable CPU __interrupts
//
DINT;
//
//Initialize the PIE control registers to their default state.
//The default state is all PIE interrupts disabled and flags
//are cleared.
//
InitPieCtrl();
//
//Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
//Initialize the PIE vector table with pointers to the shell Interrupt
//Service Routines (ISR).
//
InitPieVectTable();
EALLOW;
PieVectTable.ADCA1_INT = &adcA1ISR;
// PieVectTable.EPWM1_INT = &epwm1_isr;
EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
Gpio_select();
Setup_ePWM();
ConfigureADC();
SetupADCSoftware();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//////////////////////////
IER |= M_INT1; // Enable group 1 interrupts (ADC)
// IER |= M_INT3; // Enable group 3 interrupts (EPWM)
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// Enable PIE interrupt
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
// PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
status = SFO_INCOMPLETE;
while(status == SFO_INCOMPLETE)
{
status = SFO();
if(status == SFO_ERROR)
{
error(); // SFO function returns 2 if an error occurs & # of MEP
} // steps/coarse step exceeds maximum of 255.
}
while(1)
{
}
}
void Setup_ePWM(void)
{
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
// Setting counter mode and frequency //epwm1 for S5 as well as ADC sampling
EPwm1Regs.TBCTL.bit.FREE_SOFT = 11;
EPwm1Regs.TBPRD = TIMER_PERIOD_COUNT;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm1Regs.TBCTR = 0;
EPwm1Regs.CMPA.bit.CMPA = 0;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set output low
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; // Set output high
EPwm1Regs.TBCTL.bit.SYNCOSEL =TB_CTR_ZERO;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; //Set as a master
EPwm1Regs.TBCTL.bit.PHSDIR=TB_UP;
EPwm1Regs.DBCTL.bit.POLSEL = 2; //Active High Complementary inverted signal will be observed at ePWMB
EPwm1Regs.DBCTL.bit.OUT_MODE = 3; //fully enabled RED and FED
EPwm1Regs.DBRED.all = deadband_1A; //RED 200ns
EPwm1Regs.DBFED.all = deadband_1A; //FED 200ns
EPwm1Regs.TBCTL.bit.PRDLD= TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; //Load on CTR = Zero: Time-base counter equal to zero
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //Shadow mode
EPwm1Regs.TBPHS.all = 0;
/////// ADC SOC generation /////////////
EPwm1Regs.ETSEL.bit.SOCAEN = 1; //Epwm1A is used as start of conversion for ADC
EPwm1Regs.ETSEL.bit.SOCASEL = 1; //Enable event time based counter to zero
EPwm1Regs.ETPS.bit.SOCAPRD = 1; //at every first/third event it has to generate event
EPwm1Regs.ETCLR.bit.SOCA = 1; //Clear flag
EPwm1Regs.ETSEL.bit.INTEN = 1; //Enable ePWM Interrupt (EPWMx_INT) Generation
EPwm1Regs.ETSEL.bit.INTSEL = 1; //enable event time based counter to zero
EPwm1Regs.ETPS.bit.INTPRD = 1; //at every first/third event it has to generate event
EPwm1Regs.ETCLR.bit.INT = 1; //Clear flag
///////// Epwm2 for S6 ///////////////////
EPwm2Regs.TBCTL.bit.FREE_SOFT = 11;
EPwm2Regs.TBPRD = TIMER_PERIOD_COUNT;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm2Regs.TBCTL.bit.CLKDIV = 0;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm2Regs.TBCTR = 0;
EPwm2Regs.CMPA.bit.CMPA = 0;
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set output high
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; // Set output low
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; //Set as a master
EPwm2Regs.TBCTL.bit.PHSDIR=TB_UP;
EPwm2Regs.DBCTL.bit.POLSEL = 2; //Active High Complementary inverted signal will be observed at ePWMB
EPwm2Regs.DBCTL.bit.OUT_MODE = 3; //fully enabled RED and FED
EPwm2Regs.DBRED.all = deadband_2A; //RED 200ns
EPwm2Regs.DBFED.all = deadband_2A; //FED 200ns
EPwm2Regs.TBCTL.bit.PRDLD= TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; //Load on CTR = Zero: Time-base counter equal to zero
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //Shadow mode
EPwm2Regs.TBPHS.bit.TBPHS = 2; //Set phase angle of ePWM1 is 0
////////// Epwm3 for hrcap ///////
EPwm3Regs.TBCTL.bit.FREE_SOFT = 11;
EPwm3Regs.TBPRD = TIMER_PERIOD_COUNT;
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm3Regs.TBCTL.bit.CLKDIV = 0;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm3Regs.TBCTR = 0;
EPwm3Regs.CMPA.bit.CMPA = 230;
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set output high
EPwm3Regs.AQCTLA.bit.CAD = AQ_SET; // Set output low
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; //Set as a master
EPwm3Regs.TBCTL.bit.PHSDIR=TB_UP;
EPwm3Regs.DBCTL.bit.POLSEL = 2; //Active High Complementary inverted signal will be observed at ePWMB
EPwm3Regs.DBCTL.bit.OUT_MODE = 3; //fully enabled RED and FED
EPwm3Regs.DBRED.all = deadband_2A; //RED 200ns
EPwm3Regs.DBFED.all = deadband_2A; //FED 200ns
EPwm3Regs.TBCTL.bit.PRDLD= TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; //Load on CTR = Zero: Time-base counter equal to zero
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //Shadow mode
EPwm3Regs.TBPHS.bit.TBPHS = 2; //Set phase angle of ePWM1 is 0
///////////// Epwm4 for S1 ////////
EPwm4Regs.TBCTL.bit.FREE_SOFT = 11;
EPwm4Regs.TBPRD = TIMER_PERIOD_COUNT;
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm4Regs.TBCTL.bit.CLKDIV = 0;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm4Regs.TBCTR = 0;
EPwm4Regs.CMPA.bit.CMPA = 0;
EPwm4Regs.CMPB.bit.CMPB = 0;
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLA.bit.CBU = AQ_SET;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; //Set as a master
EPwm4Regs.TBCTL.bit.PHSDIR=TB_UP;
EPwm4Regs.DBCTL.bit.POLSEL = 2; //Active High Complementary inverted signal will be observed at ePWMB
EPwm4Regs.DBCTL.bit.OUT_MODE = 3; //fully enabled RED and FED
EPwm4Regs.DBRED.all = deadband; //RED 200ns
EPwm4Regs.DBFED.all = deadband; //FED 200ns
EPwm4Regs.TBCTL.bit.PRDLD= TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; //Load on CTR = Zero: Time-base counter equal to zero
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //Shadow mode
EPwm4Regs.TBPHS.bit.TBPHS = 0; //Set phase angle of ePWM1 is 0
///////////// Epwm5 for S2 /////////////
EPwm5Regs.TBCTL.bit.FREE_SOFT = 11;
EPwm5Regs.TBPRD = TIMER_PERIOD_COUNT;
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm5Regs.TBCTL.bit.CLKDIV = 0;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm5Regs.TBCTR = 0;
EPwm5Regs.CMPA.bit.CMPA = 0;
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set output high
EPwm5Regs.AQCTLA.bit.CAD = AQ_SET; // Set output low
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; //Set as a master
EPwm5Regs.TBCTL.bit.PHSDIR=TB_UP;
EPwm5Regs.DBCTL.bit.POLSEL = 2; //Active High Complementary inverted signal will be observed at ePWMB
EPwm5Regs.DBCTL.bit.OUT_MODE = 3; //fully enabled RED and FED
EPwm5Regs.DBRED.all = deadband; //RED 200ns
EPwm5Regs.DBFED.all = deadband; //FED 200ns
EPwm5Regs.TBCTL.bit.PRDLD= TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; //Load on CTR = Zero: Time-base counter equal to zero
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //Shadow mode
EPwm5Regs.TBPHS.bit.TBPHS = 0; //Set phase angle of ePWM1 is 0
////////// Epwm6 for S3 ///////////
EPwm6Regs.TBCTL.bit.FREE_SOFT = 11;
EPwm6Regs.TBPRD = TIMER_PERIOD_COUNT;
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm6Regs.TBCTL.bit.CLKDIV = 0;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm6Regs.TBCTR = 0;
EPwm6Regs.CMPA.bit.CMPA = 0;
EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set output high
EPwm6Regs.AQCTLA.bit.CAD = AQ_SET; // Set output low
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; //Set as a master
EPwm6Regs.TBCTL.bit.PHSDIR=TB_UP;
EPwm6Regs.DBCTL.bit.POLSEL = 2; //Active High Complementary inverted signal will be observed at ePWMB
EPwm6Regs.DBCTL.bit.OUT_MODE = 3; //fully enabled RED and FED
EPwm6Regs.DBRED.all = deadband; //RED 200ns
EPwm6Regs.DBFED.all = deadband; //FED 200ns
EPwm6Regs.TBCTL.bit.PRDLD= TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register
EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; //Load on CTR = Zero: Time-base counter equal to zero
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //Shadow mode
EPwm6Regs.TBPHS.bit.TBPHS = 0; //Set phase angle of ePWM1 is 0
///////// Epwm7 for ADC ////// Only for hybrid modulation program
EPwm7Regs.TBCTL.bit.FREE_SOFT = 11;
EPwm7Regs.TBPRD = TIMER_PERIOD_COUNT;
EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm7Regs.TBCTL.bit.CLKDIV = 0;
EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm7Regs.TBCTR = 0;
EPwm7Regs.CMPA.bit.CMPA = 0;
EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set output high
EPwm7Regs.AQCTLA.bit.CAD = AQ_SET; // Set output low
EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE; //Set as a master
EPwm7Regs.TBCTL.bit.PHSDIR=TB_UP;
EPwm7Regs.DBCTL.bit.POLSEL = 2; //Active High Complementary inverted signal will be observed at ePWMB
EPwm7Regs.DBCTL.bit.OUT_MODE = 3; //fully enabled RED and FED
EPwm7Regs.DBRED.all = deadband; //RED 200ns
EPwm7Regs.DBFED.all = deadband; //FED 200ns
EPwm7Regs.TBCTL.bit.PRDLD= TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register
EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; //Load on CTR = Zero: Time-base counter equal to zero
EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //Shadow mode
EPwm7Regs.TBPHS.bit.TBPHS = 0; //Set phase angle of ePWM1 is 0
////////// Epwm8 for S4 ///////////
EPwm8Regs.TBCTL.bit.FREE_SOFT = 11;
EPwm8Regs.TBPRD = TIMER_PERIOD_COUNT;
EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm8Regs.TBCTL.bit.CLKDIV = 0;
EPwm8Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm8Regs.TBCTR = 0;
EPwm8Regs.CMPA.bit.CMPA = 0;
EPwm8Regs.CMPB.bit.CMPB = 0;
EPwm8Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
EPwm8Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;
EPwm8Regs.AQCTLA.bit.CAD = AQ_NO_ACTION;
EPwm8Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;
EPwm8Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm8Regs.TBCTL.bit.PHSEN = TB_ENABLE; //Set as a master
EPwm8Regs.TBCTL.bit.PHSDIR=TB_UP;
EPwm8Regs.DBCTL.bit.POLSEL = 2; //Active High Complementary inverted signal will be observed at ePWMB
EPwm8Regs.DBCTL.bit.OUT_MODE = 3; //fully enabled RED and FED
EPwm8Regs.DBRED.all = 0; //RED 200ns
EPwm8Regs.DBFED.all = 0; //FED 200ns
EPwm8Regs.TBCTL.bit.PRDLD= TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register
EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; //Load on CTR = Zero: Time-base counter equal to zero
EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE; //Shadow mode
EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; //Load on CTR = Zero: Time-base counter equal to zero
EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE; //Shadow mode
EPwm8Regs.TBPHS.bit.TBPHS = 0; //Set phase angle of ePWM1 is 0
EALLOW;
Clb1LogicCfgRegs.CLB_LUT4_IN0.bit.SEL_0 = 24U; // i0 <- CLB_IN0
Clb1LogicCfgRegs.CLB_LUT4_IN1.bit.SEL_0 = 25U; // i1 <- CLB_IN1
// The following will configure the LUT to be used to logically AND the two signals
Clb1LogicCfgRegs.CLB_LUT4_FN1_0.bit.FN0 = 0x8888U;
// The following will pass the AND'd signal from the LUT and output it via the OUTLUT
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN0 = 7U;
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.FN = 0xAAU;
EDIS;
// EALLOW;
// InputXbarRegs.INPUT1SELECT=4;
// EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0=0;
// EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;
//
//
// EPwm8Regs.DCTRIPSEL.bit.DCAHCOMPSEL= 3; // TRIPIN4
// EPwm8Regs.TZDCSEL.bit.DCAEVT1 = 2; // Digital Compare Output A Event 1 Selection DCAH = high, DCAL = don't care
// EPwm8Regs.DCACTL.bit.EVT1SRCSEL = 0; // Unfiltered
// EPwm8Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; // Asynchronous
// EPwm8Regs.AQTSRCSEL.bit.T1SEL=0;
// EPwm8Regs.AQCTLA2.bit.T1D=AQ_SET;
// EPwm8Regs.AQCTLA2.bit.T1U=AQ_SET;
// EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
}
void Gpio_select(void)
{
EALLOW;
//setup EPWM PINS
// Disable internal pull-up for the selected output pins for reduced power
//epwm1 for S5
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A)
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B)
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B
//epwm2 for S6
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A)
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B)
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO2 as EPWM2B
//epwm3 //for hrcap
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO0 (EPWM3A)
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO1 (EPWM3B)
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO0 as hrcap
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO2 as hrcap
//epwm4 for S1
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1;
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1;
//epwm5 for S2
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A)
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO (EPWM5B)
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;
//epwm6 for S3
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A)
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO1 (EPWM6B)
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;
//epwm7 for ADC
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO10 (EPWM7A)
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO1 (EPWM7B)
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO10 as EPWM7A
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1;
//epwm8 for S4
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO12 (EPWM8A)
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 1; // Disable pull-up on GPIO (EPWM8B)
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO12 as EPWM8A
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO12 as EPWM8B
//epwm8 as GPIO
// GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0; // Configure GPIO12 as EPWM8A
// GpioCtrlRegs.GPADIR.bit.GPIO14=1;
// GpioDataRegs.GPACLEAR.bit.GPIO14=1;
//
// GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; // Configure GPIO12 as EPWM8B
// GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; // Disable pull-up on GPIO (EPWM8B)
// GpioDataRegs.GPBCLEAR.bit.GPIO32=1;
//Setting GPIO for Relay operation
GpioCtrlRegs.GPAMUX1.bit.GPIO15=0; //Setting pin as GPIO for Relay
GpioCtrlRegs.GPADIR.bit.GPIO15=1; //setting pin as output pin
GpioDataRegs.GPACLEAR.bit.GPIO15=1; //Clearing the GPIO
//Setting GPIO for internal time operation
GpioCtrlRegs.GPAMUX2.bit.GPIO26=0; //Setting pin as GPIO
GpioCtrlRegs.GPADIR.bit.GPIO26=1; //setting pin as output pin
GpioDataRegs.GPACLEAR.bit.GPIO26=1; //Clearing the GPIO
EDIS;
}
void ConfigureADC(void)
{
// initADC - Function to configure and power up ADCA.
//
SetVREF(ADC_ADCA, ADC_INTERNAL, ADC_VREF3P3); // Setup VREF as internal
EALLOW;
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; // Set ADCCLK divider to /4
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Set pulse positions to late
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC and then delay for 1 ms
EDIS;
DELAY_US(1000);
}
void SetupADCSoftware(void)
{
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; // Grid voltage sensor (A0)
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 9; //sample duration of 10 SYSCLK cycles (100ns/10ns)
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; // Trigger on ePWM6 SOCA
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; // Grid current sensor (A1)
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
// AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3; // Grid current sensor (A3)
// AdcaRegs.ADCSOC3CTL.bit.ACQPS = 9;
// AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 17;
AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3; // DC current sensor (mid point)
AdcaRegs.ADCSOC3CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 5;
AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4; //DC link voltage sensor (A4)
AdcaRegs.ADCSOC4CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = 5;
AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5; // DC current sensor (A5)
AdcaRegs.ADCSOC5CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC5CTL.bit.TRIGSEL = 5;
AdcaRegs.ADCSOC6CTL.bit.CHSEL = 6; // DC current sensor (A6)
AdcaRegs.ADCSOC6CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC6CTL.bit.TRIGSEL = 5;
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 6; // End of SOC3 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared
EDIS;
}
__interrupt void adcA1ISR(void)
{
v_a=250;
EPwm1Regs.CMPA.bit.CMPA = v_a;
EPwm2Regs.CMPA.bit.CMPA = v_a;
EPwm4Regs.DBRED.all = 0;
EPwm4Regs.CMPA.bit.CMPA = v_a;
EPwm4Regs.CMPB.bit.CMPB = v_a+deadband;
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLA.bit.CBU = AQ_SET;
// EPwm8Regs.DBRED.all = 0;
// EPwm8Regs.DBFED.all = 0;
// EPwm8Regs.CMPA.bit.CMPA = v_a;
// EPwm8Regs.CMPB.bit.CMPB = v_a+deadband;
// EPwm8Regs.CMPC=v_a-deadband;
// EPwm8Regs.AQCTLA.bit.CAD = AQ_CLEAR;
// EPwm8Regs.AQCTLA.bit.CAU = AQ_CLEAR;
// EPwm8Regs.AQCTLA.bit.CBU = AQ_SET;
// EPwm8Regs.AQCTLA2.bit.T1D=AQ_SET;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT1)
{
AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //clear INT1 overflow flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
}
PieCtrlRegs.PIEACK.bit.ACK1 = PIEACK_GROUP1;
}
void error (void)
{
ESTOP0; // Stop here and handle error
}
Hi Akash,
The expert is currently out of the office until mid-next week and will get back to you as soon as possible. Thank you for your patience.
Best Regards,
Aishwarya
Hi Akash,
I apologize as I was out of the office last week. Thank you for your patience. As I am reading through your code snippet I noticed that you are configuring GPIO's as EPWM's. I assume that you are then attempting to input these GPIO outputs to the CLB to do the logical operations?
Kind regards,
AJ Favela
